On 26.01.2021 12:06, Roger Pau Monne wrote: > Plain MSI doesn't allow caching the MSI address and data fields while > the capability is enabled and not masked, hence we need to allow any > changes to those fields to update the binding of the interrupt. For > reference, the same doesn't apply to MSI-X that is allowed to cache > the data and address fields while the entry is unmasked, see section > 6.8.3.5 of the PCI Local Bus Specification 3.0. > > Allowing such updates means that a guest can write an invalid address > (ie: all zeros) and then a valid one, so the PIRQs shouldn't be > unmapped when the interrupt cannot be bound to the guest, since > further updates to the address or data fields can result in the > binding succeeding.
IOW the breakage from the other patch was because rubbish was written first, and suitable data was written later on? I didn't think core PCI code in Linux would do such, which would make me suspect a driver having custom MSI handling code ... > Modify the vPCI MSI arch helpers to track whether the interrupt is > bound, and make failures in vpci_msi_update not unmap the PIRQ, so > that further calls can attempt to bind the PIRQ again. > > Note this requires some modifications to the MSI-X handlers, but there > shouldn't be any functional changes in that area. > > Signed-off-by: Roger Pau Monné <roger....@citrix.com> Reviewed-by: Jan Beulich <jbeul...@suse.com> Am I understanding correctly that this change is independent of the initial 2 patches (where I have reservations), and hence it could go in ahead of them (or all alone)? Jan
