Am Mittwoch, 24. Mai 2006 06:07 schrieb Tian, Kevin: > >From: Magenheimer, Dan (HP Labs Fort Collins) > >Sent: 2006年5月23日 22:40 > >> > > > May it be that XEN_HYPER_ITC_D and XEN_HYPER_ITC_I are > >in > >> > > > >> > > the reverse > >> > > > >> > > > order? > >> > > > >> > > Good catch. > >> > > > >> > > Feel free to send a patch. > >> > > >> > Does this code ever get executed? The VHPT is pinned by > >> > a TR, correct? > > > >Oops, Xen's VHPT is pinned, the guest's isn't pinned. > > > >> For sure it is strange we never hit this bug ;-) > > > >Yes, it looks like the faulty code should get executed. > >Maybe it quickly > >fixes itself because the wrong vtlb gets inserted, > >then another miss immediately occurs which is not > >a VHPT fault so the correct vtlb gets inserted. > > Definitely. The key point is that vhpt entry is inserted after above bogus > place and then TLB miss immediately happens after resuming with > hardware triggered to walk vhpt table by inserting desired mapping. > Above two insertions are only optimization code which don't hurt > anything even not being there. > > > > >Anyway, yes, please submit a patch! > > > >Dan > > > > Yes, patch is needed. > > Thanks, > Kevin >
Hi, I hope the patch is in the right format. Thanks. Dietmar.
swap XEN_HYPER_ITC_D and XEN_HYPER_ITC_I Signed-off-by Dietmar Hahn <[EMAIL PROTECTED]> diff -r 303e1b6bf727 linux-2.6-xen-sparse/arch/ia64/xen/xenivt.S --- a/linux-2.6-xen-sparse/arch/ia64/xen/xenivt.S Sun May 21 07:49:46 2006 -0600 +++ b/linux-2.6-xen-sparse/arch/ia64/xen/xenivt.S Wed May 24 12:46:13 2006 +0200 @@ -206,9 +206,9 @@ ENTRY(vhpt_miss) mov r24=r8 mov r8=r18 ;; -(p10) XEN_HYPER_ITC_D - ;; -(p11) XEN_HYPER_ITC_I +(p10) XEN_HYPER_ITC_I + ;; +(p11) XEN_HYPER_ITC_D ;; mov r8=r24 ;;
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