On 30/08/06, Dmitry Adamushko <[EMAIL PROTECTED]> wrote:
Nop, it looks wrong. Ignore this part :)
(cache line == 128 bits) let's say cacheline[4]
int a = 1; // e.g. &a == 0xabcd0004
this part of memory is currently not in the cache. So :
1) [0xabcd0000, 0xabcd0010] == 128 bits is loaded from memory into cacheline.
Nop, it looks wrong. Ignore this part :)
2) then 1 is loaded into cacheline[1]
3) [ write-through ] ---> sync with memory
or
[ write-back ] ---> delay synching
?
Jan
--
Best regards,Dmitry Adamushko
--
Best regards,
Dmitry Adamushko
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