On 2012-09-17 08:30, Gilles Chanteperdrix wrote: > > Hi, > > looking at x86 latencies, I found that what was taking long on my atom > was masking the fasteoi interrupts at IO-APIC level. So, I experimented > an idea: masking at LAPIC level instead of IO-APIC, by using the "task > priority" register. This seems to improve latencies on my atom: > > http://sisyphus.hd.free.fr/~gilles/core-3.4-latencies/atom.png > > This implies splitting the LAPIC vectors in a high priority and low > priority sets, the final implementation would use ipipe_enable_irqdesc > to detect a high priority domain, and change the vector at that time. > > This also improves the latencies on my old PIII with a VIA chipset, but > it generates spurious interrupts (I do not know if it really is a > matter, as handling a spurious interrupt is still faster than masking an > IO-APIC interrupt), the spurious interrupts in that case are a > documented behaviour of the LAPIC. > > Is there any interest in pursuing this idea, or are x86 with slow > IO-APIC the exception more than the rule, or having to split the vector > space appears too great a restriction?
Line-based interrupts are legacy, of decreasing relevance for PCI devices - likely what we are primarily interesting in here - due to MSI. So I tend to say "don't worry", specifically as fiddling with vector allocations will require yet another round of invasive changes to the IRQ subsystem of Linux. Jan -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 259 bytes Desc: OpenPGP digital signature URL: <http://www.xenomai.org/pipermail/xenomai/attachments/20120917/d94c6ca9/attachment.pgp> _______________________________________________ Xenomai mailing list Xenomai@xenomai.org http://www.xenomai.org/mailman/listinfo/xenomai
