The problem is the fact that the arm twd irq (for example) is masked on that specific core inside gic, but the ipipe is locking it globally.
According to GIC architecture specification https://www.cl.cam.ac.uk/research/srg/han/ACS-P35/zynq/arm_gic_architecture_specification.pdf Section 2.2.1 ... Interrupt numbers ID0-ID31 are used for interrupts that are private to a CPU interface. These interrupts are banked in the Distributor. A banked interrupt is one where the Distributor can have multiple interrupts with the same ID. A banked interrupt is identified uniquely by its ID number and its associated CPU interface number. Of the banked interrupt IDs: — ID0-ID15 are used for SGIs — ID16-ID31 are used for PPIs In a multiprocessor system: — A PPI is forwarded to a particular CPU interface, and is private to that interface. In prioritizing interrupts for a CPU interface the Distributor does not consider PPIs that relate to other interfaces. ... In our case, we're talking about ID29 (linux mapped 16). In kernel/ipipe/core.c, in function __ipipe_lock_irq the control bits should either be set per cpu and not globally if the hwirq is less than 31. A suggestion would be to use the NR_CPUS bits from ipd->irqs[irq].control to mark the lock on a per cpu basis and then depending on the type of the irq set the corresponding bits for each (or all, in case SPIs) cpu. And then, when checking if locked (in __ipipe_set_irq_pending and __ipipe_do_sync_stage) include the cpu in the condition. That should be all. I'll try to come up with a patch later. I just wanted to point out the problem here. Abel -- _______________________________________________ Xenomai mailing list [email protected] https://xenomai.org/mailman/listinfo/xenomai
