On 13.10.20 09:45, hongzha1 wrote:
> Before calling irq_post_oob, interrupts must be hard disabled
> in the cpu. But irq_inject_pipeline would handle it internally.
> 
> Signed-off-by: hongzha1 <hongzhan.c...@intel.com>
> 
> diff --git a/kernel/cobalt/arch/x86/include/asm/xenomai/thread.h 
> b/kernel/cobalt/arch/x86/include/asm/xenomai/thread.h
> index af3433e8e..46294036b 100644
> --- a/kernel/cobalt/arch/x86/include/asm/xenomai/thread.h
> +++ b/kernel/cobalt/arch/x86/include/asm/xenomai/thread.h
> @@ -23,6 +23,7 @@
>  #include <asm-generic/xenomai/thread.h>
>  #include <asm/xenomai/wrappers.h>
>  #include <asm/traps.h>
> +#include <linux/irq_pipeline.h>
>  
>  #ifndef IPIPE_X86_FPU_EAGER
>  #if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0)
> @@ -90,7 +91,7 @@ static inline int xnarch_escalate(void)
>  {
>       if (running_inband()) {
>               /* orginal xenomai domain equals oob stage */
> -             irq_post_oob(cobalt_pipeline.escalate_virq);
> +             irq_inject_pipeline(cobalt_pipeline.escalate_virq);
>               return 1;
>       }
>  /*   if (ipipe_root_p) {
> 

Thanks, both this and the enable_oob_stage applied.

Jan

-- 
Siemens AG, T RDA IOT
Corporate Competence Center Embedded Linux

Reply via email to