On Fri, 24 Jan 2003, Cedric De Wilde wrote: > On Fri, Jan 24, 2003 at 01:14:18AM -0800, hy0 wrote: > > Thanks for the explanations, now I can see what this is about. However I > > still have some concerns about this code. > > Indeed, Radeon chips do have 0x1c0 (misnamed MPP_TB_CONFIG) as SEPROM_CNTL > > register. Modifying/restoring its SCK_PRESCALE field is unlikely to be the > > cause of this screen corruption problem. > > In the current code path, even for a properly POSTed card, MEM_CNTL is set > > to zero and then restored back. This step may cause some side effect to the > > memory controller. Properly initializing MEM_CNTL/MEM_SIZE should take > > several steps (I may miss something): 1. wait for memory control idle > > (MC_STATUS). 2. configure each channel (MEM_CNTL). 3. reset memory > > (MEM_SDRAM_MOD_REG). 4. check if each channel works correctly. Simply > > setting MEM_CNTL to zero and then restoring it back may put memory > > controller in some bad state.
To me, this only means more registers need to be saved, and later restored in a specific order. It should be possible to determine such a sequence from the BIOS init code. It would be for Mach64 and Rage128 variants, I know. But I don't happen to have a Radeon BIOS Kit at the moment. > > Since Cedric doesn't seem to have this problem > > with old CVS code, maybe he can try to change the current CVS code from > > #if 0/* !defined(__alpha__) */ > > back to > > #if !defined(__alpha__) > > See if it can make any difference. At least we can rule out MEM_CNTL related > > code being the cause. > Cool, it work, thanks. There was only a bug in the keyboard mapping but > it's not related. That's fine for the purpose of nailing down the problem. But I don't see this as a good solution. Marc. +----------------------------------+-----------------------------------+ | Marc Aurele La France | work: 1-780-492-9310 | | Computing and Network Services | fax: 1-780-492-1729 | | 352 General Services Building | email: [EMAIL PROTECTED] | | University of Alberta +-----------------------------------+ | Edmonton, Alberta | | | T6G 2H1 | Standard disclaimers apply | | CANADA | | +----------------------------------+-----------------------------------+ XFree86 Core Team member. ATI driver and X server internals. _______________________________________________ XFree86 mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/xfree86
