Modified table attached to this email.
On 08/08/2012 12:14 PM, Jennita Catherine wrote:
Hello,
I have a query regarding XMLmind Editor.
Consider the following table created in xml:
<para><table>
<title>Map00 Address Mapping</title>
<tgroup cols="3">
<thead>
<row>
<entry align="center">Address Bits</entry>
<entry align="center">Name</entry>
<entry align="center">Description</entry>
</row>
</thead>
<tbody>
<row condition="not.FLASH_BANK_LOC_29_27">
<entry condition="FLASH_BANK_LOC_25_24">31:28</entry>
<entry condition="FLASH_BANK_LOC_26_24">31:29</entry>
<entry condition="FLASH_BANK_LOC_27_26">31:30</entry>
<entry condition="FLASH_BANK_LOC_28_26">31</entry>
<entry>port_int_add</entry>
<entry><para>The host interface port address.</para></entry>
</row>
<row>
<entry condition="FLASH_BANK_LOC_25_24">27:26</entry>
<entry condition="FLASH_BANK_LOC_26_24">28:27</entry>
<entry condition="FLASH_BANK_LOC_27_26">29:28</entry>
<entry condition="FLASH_BANK_LOC_28_26">30:29</entry>
<entry condition="FLASH_BANK_LOC_29_27">31:30</entry>
<entry>CMD_MAP</entry>
<entry>00 = Read or Wr>
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ite of the Page Buffer</entry>
</row>
<row>
<entry condition="FLASH_BANK_LOC_25_24">25:24</entry>
<entry condition="FLASH_BANK_LOC_26_24">26:24</entry>
<entry condition="FLASH_BANK_LOC_27_26">27:26</entry>
<entry condition="FLASH_BANK_LOC_28_26">28:26</entry>
<entry condition="FLASH_BANK_LOC_29_27">29:27</entry>
<entry>BANK_SEL</entry>
<entry><para>Selects the bank for this
access.</para></entry>
</row>
<row condition="not.INDEXED_ADDRESSING">
<entry condition="not.FLASH_24BIT_BLK_PG_ADDR">23:16</entry>
<entry condition="FLASH_24BIT_BLK_PG_ADDR">25:16</entry>
<entry>Reserved</entry>
<entry>These bits should be tied low.</entry>
</row>
<row condition="INDEXED_ADDRESSING">
<entry condition="not.FLASH_BANK_LOC_29_27">23:16</entry>
<entry condition="FLASH_BANK_LOC_29_27">26:16</entry>
<entry>Reserved</entry>
<entry>These bits should be tied low.</entry>
</row>
<row>
<entry>15:R</entry>
<entry>BUFF_ADDR</entry>
<entry><para>The host interface data bus width-aligned
buffer address on the memory device. </para></entry>
</row>
<row>
<entry>(R-1):0</entry>
<entry>Reserved</entry>
<entry><para>These bits should be tied low.</para> <para>If
the controller slave interface data bus width is 16 : R
Value is 1</para> <para>If the controller slave interface
data bus width is 32 : R Value is 2</para> <para>If the
controller slave interface data bus width is 64 : R
Value is
3</para> <para>If the controller slave interface data bus
width is 128: R Value is 4</para></entry>
</row>
</tbody>
</tgroup>
</table></para>
When I try to generate a pdf, I could see many extra columns to this
table, instead of just 3 as specified.
when I reopen the xml file, I could see that the number of tgroup has
also changed automatically, i.e. 6.
Why does it work this way? Is there a problem with the setup or am I
doing something wrong?
Regards,
Jen
<?xml version="1.0"?>
<table>
<title>Map00 Address Mapping</title>
<tgroup cols="3">
<thead>
<row>
<entry align="center">Address Bits</entry>
<entry align="center">Name</entry>
<entry align="center">Description</entry>
</row>
</thead>
<tbody>
<row condition="not.FLASH_BANK_LOC_29_27">
<entry>
<para condition="FLASH_BANK_LOC_25_24">31:28</para>
<para condition="FLASH_BANK_LOC_26_24">31:29</para>
<para condition="FLASH_BANK_LOC_27_26">31:30</para>
<para condition="FLASH_BANK_LOC_28_26">31</para>
</entry>
<entry>port_int_add</entry>
<entry><para>The host interface port address.</para></entry>
</row>
<row>
<entry>
<para condition="FLASH_BANK_LOC_25_24">27:26</para>
<para condition="FLASH_BANK_LOC_26_24">28:27</para>
<para condition="FLASH_BANK_LOC_27_26">29:28</para>
<para condition="FLASH_BANK_LOC_28_26">30:29</para>
<para condition="FLASH_BANK_LOC_29_27">31:30</para>
</entry>
<entry>CMD_MAP</entry>
<entry>00 = Read or Write of the Page Buffer</entry>
</row>
<row>
<entry>
<para condition="FLASH_BANK_LOC_25_24">25:24</para>
<para condition="FLASH_BANK_LOC_26_24">26:24</para>
<para condition="FLASH_BANK_LOC_27_26">27:26</para>
<para condition="FLASH_BANK_LOC_28_26">28:26</para>
<para condition="FLASH_BANK_LOC_29_27">29:27</para>
</entry>
<entry>BANK_SEL</entry>
<entry><para>Selects the bank for this
access.</para></entry>
</row>
<row condition="not.INDEXED_ADDRESSING">
<entry>
<para condition="not.FLASH_24BIT_BLK_PG_ADDR">23:16</para>
<para condition="FLASH_24BIT_BLK_PG_ADDR">25:16</para>
</entry>
<entry>Reserved</entry>
<entry>These bits should be tied low.</entry>
</row>
<row condition="INDEXED_ADDRESSING">
<entry>
<para condition="not.FLASH_BANK_LOC_29_27">23:16</para>
<para condition="FLASH_BANK_LOC_29_27">26:16</para>
</entry>
<entry>Reserved</entry>
<entry>These bits should be tied low.</entry>
</row>
<row>
<entry>15:R</entry>
<entry>BUFF_ADDR</entry>
<entry><para>The host interface data bus width-aligned
buffer address on the memory device. </para></entry>
</row>
<row>
<entry>(R-1):0</entry>
<entry>Reserved</entry>
<entry><para>These bits should be tied low.</para> <para>If
the controller slave interface data bus width is 16 : R
Value is 1</para> <para>If the controller slave interface
data bus width is 32 : R Value is 2</para> <para>If the
controller slave interface data bus width is 64 : R Value is
3</para> <para>If the controller slave interface data bus
width is 128: R Value is 4</para></entry>
</row>
</tbody>
</tgroup>
</table>
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