On 2020-03-19 8:54 p.m., Marek Olšák wrote: > On Thu., Mar. 19, 2020, 06:51 Daniel Vetter, <dan...@ffwll.ch> > wrote: >> >> Yeah, this is entirely about the programming model visible to >> userspace. There shouldn't be any impact on the driver's choice of >> a top vs. bottom of the gpu pipeline used for synchronization, >> that's entirely up to what you're hw/driver/scheduler can pull >> off. >> >> Doing a full gfx pipeline flush for shared buffers, when your hw >> can do be, sounds like an issue to me that's not related to this >> here at all. It might be intertwined with amdgpu's special >> interpretation of dma_resv fences though, no idea. We might need to >> revamp all that. But for a userspace client that does nothing fancy >> (no multiple render buffer targets in one bo, or vk style "I write >> to everything all the time, perhaps" stuff) there should be 0 perf >> difference between implicit sync through dma_resv and explicit sync >> through sync_file/syncobj/dma_fence directly. >> >> If there is I'd consider that a bit a driver bug. > > Last time I checked, there was no fence sync in gnome shell and > compiz after an app passes a buffer to it.
They are not required (though encouraged) to do that. > So drivers have to invent hacks to work around it and decrease > performance. It's not a driver bug. > > Implicit sync really means that apps and compositors don't sync, so > the driver has to guess when it should sync. Making implicit sync work correctly is ultimately the kernel driver's responsibility. It sounds like radeonsi is having to work around the amdgpu/radeon kernel driver(s) not fully living up to this responsibility. -- Earthling Michel Dänzer | https://redhat.com Libre software enthusiast | Mesa and X developer _______________________________________________ xorg-devel@lists.x.org: X.Org development Archives: http://lists.x.org/archives/xorg-devel Info: https://lists.x.org/mailman/listinfo/xorg-devel
