https://bugs.freedesktop.org/show_bug.cgi?id=98046
--- Comment #9 from James Cameron <qu...@laptop.org> ---
Other than reverting the series in comment 4, I've no solution. Once I had
that workaround, I was mostly happy. I wanted to find the underlying problem
and upstream it, but ran out of time.
At one stage I was using "avivotool regs pll1" to confirm the PLL registers,
comparing between last working kernel version, latest kernel, and my kernel
with the series reverted.
My notes have outstanding questions that I didn't get to resolve;
1. how to achieve a dot clock of 360000 instead of 366660, given that 360000
works for me?
2. why is RADEON_PLL_PREFER_LOW_REF_DIV set given that the bit is only used
when RADEON_PLL_LEGACY is set?
3. why set RADEON_PLL_PREFER_MINM_OVER_MAXP given that it limits the ref_div to
7 yet the system has already chosen 2 instead of 5.
Hope that helps.
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