r128_crtc.c is the more logical place this function should be located. R128PLLWaitForReadUpdateComplete and R128PLLWriteUpdate functions were moved as well.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com> --- src/r128_crtc.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/r128_driver.c | 89 ------------------------------------------------------- 2 files changed, 89 insertions(+), 89 deletions(-) diff --git a/src/r128_crtc.c b/src/r128_crtc.c index 3afded9..ef44d0f 100644 --- a/src/r128_crtc.c +++ b/src/r128_crtc.c @@ -443,6 +443,95 @@ void R128InitPLL2Registers(xf86CrtcPtr crtc, R128SavePtr save, save->htotal_cntl2 = 0; } +static void R128PLLWaitForReadUpdateComplete(ScrnInfoPtr pScrn) +{ + while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R); +} + +static void R128PLLWriteUpdate(ScrnInfoPtr pScrn) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + + while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R); + + OUTPLLP(pScrn, R128_PPLL_REF_DIV, R128_PPLL_ATOMIC_UPDATE_W, + ~R128_PPLL_ATOMIC_UPDATE_W); + +} + +/* Write PLL registers. */ +void R128RestorePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr restore) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + + + OUTPLLP(pScrn, R128_VCLK_ECP_CNTL, + R128_VCLK_SRC_SEL_CPUCLK, + ~(R128_VCLK_SRC_SEL_MASK)); + + OUTPLLP(pScrn, + R128_PPLL_CNTL, + R128_PPLL_RESET + | R128_PPLL_ATOMIC_UPDATE_EN + | R128_PPLL_VGA_ATOMIC_UPDATE_EN, + ~(R128_PPLL_RESET + | R128_PPLL_ATOMIC_UPDATE_EN + | R128_PPLL_VGA_ATOMIC_UPDATE_EN)); + + OUTREGP(R128_CLOCK_CNTL_INDEX, R128_PLL_DIV_SEL, ~(R128_PLL_DIV_SEL)); + +/* R128PLLWaitForReadUpdateComplete(pScrn);*/ + OUTPLLP(pScrn, R128_PPLL_REF_DIV, + restore->ppll_ref_div, ~R128_PPLL_REF_DIV_MASK); +/* R128PLLWriteUpdate(pScrn); + + R128PLLWaitForReadUpdateComplete(pScrn);*/ + OUTPLLP(pScrn, R128_PPLL_DIV_3, + restore->ppll_div_3, ~R128_PPLL_FB3_DIV_MASK); +/* R128PLLWriteUpdate(pScrn);*/ + OUTPLLP(pScrn, R128_PPLL_DIV_3, + restore->ppll_div_3, ~R128_PPLL_POST3_DIV_MASK); + + R128PLLWriteUpdate(pScrn); + R128PLLWaitForReadUpdateComplete(pScrn); + + OUTPLLP(pScrn, R128_PPLL_DIV_0, + restore->ppll_div_0, ~R128_PPLL_FB0_DIV_MASK); +/* R128PLLWriteUpdate(pScrn);*/ + OUTPLLP(pScrn, R128_PPLL_DIV_0, + restore->ppll_div_0, ~R128_PPLL_POST0_DIV_MASK); + + R128PLLWriteUpdate(pScrn); + R128PLLWaitForReadUpdateComplete(pScrn); + + OUTPLL(R128_HTOTAL_CNTL, restore->htotal_cntl); +/* R128PLLWriteUpdate(pScrn);*/ + + OUTPLLP(pScrn, R128_PPLL_CNTL, 0, ~(R128_PPLL_RESET + | R128_PPLL_SLEEP + | R128_PPLL_ATOMIC_UPDATE_EN + | R128_PPLL_VGA_ATOMIC_UPDATE_EN)); + + R128TRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", + restore->ppll_ref_div, + restore->ppll_div_3, + restore->htotal_cntl, + INPLL(pScrn, R128_PPLL_CNTL))); + R128TRACE(("Wrote: rd=%d, fd=%d, pd=%d\n", + restore->ppll_ref_div & R128_PPLL_REF_DIV_MASK, + restore->ppll_div_3 & R128_PPLL_FB3_DIV_MASK, + (restore->ppll_div_3 & R128_PPLL_POST3_DIV_MASK) >> 16)); + + usleep(5000); /* let the clock lock */ + + OUTPLLP(pScrn, R128_VCLK_ECP_CNTL, + R128_VCLK_SRC_SEL_PPLLCLK, + ~(R128_VCLK_SRC_SEL_MASK)); + +} + static void r128_crtc_load_lut(xf86CrtcPtr crtc); diff --git a/src/r128_driver.c b/src/r128_driver.c index 66920fb..fd246c1 100644 --- a/src/r128_driver.c +++ b/src/r128_driver.c @@ -2199,23 +2199,6 @@ void R128RestoreLVDSRegisters(ScrnInfoPtr pScrn, R128SavePtr restore) } } -static void R128PLLWaitForReadUpdateComplete(ScrnInfoPtr pScrn) -{ - while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R); -} - -static void R128PLLWriteUpdate(ScrnInfoPtr pScrn) -{ - R128InfoPtr info = R128PTR(pScrn); - unsigned char *R128MMIO = info->MMIO; - - while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R); - - OUTPLLP(pScrn, R128_PPLL_REF_DIV, R128_PPLL_ATOMIC_UPDATE_W, - ~R128_PPLL_ATOMIC_UPDATE_W); - -} - static void R128PLL2WaitForReadUpdateComplete(ScrnInfoPtr pScrn) { while (INPLL(pScrn, R128_P2PLL_REF_DIV) & R128_P2PLL_ATOMIC_UPDATE_R); @@ -2233,78 +2216,6 @@ static void R128PLL2WriteUpdate(ScrnInfoPtr pScrn) ~(R128_P2PLL_ATOMIC_UPDATE_W)); } -/* Write PLL registers. */ -void R128RestorePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr restore) -{ - R128InfoPtr info = R128PTR(pScrn); - unsigned char *R128MMIO = info->MMIO; - - - OUTPLLP(pScrn, R128_VCLK_ECP_CNTL, - R128_VCLK_SRC_SEL_CPUCLK, - ~(R128_VCLK_SRC_SEL_MASK)); - - OUTPLLP(pScrn, - R128_PPLL_CNTL, - R128_PPLL_RESET - | R128_PPLL_ATOMIC_UPDATE_EN - | R128_PPLL_VGA_ATOMIC_UPDATE_EN, - ~(R128_PPLL_RESET - | R128_PPLL_ATOMIC_UPDATE_EN - | R128_PPLL_VGA_ATOMIC_UPDATE_EN)); - - OUTREGP(R128_CLOCK_CNTL_INDEX, R128_PLL_DIV_SEL, ~(R128_PLL_DIV_SEL)); - -/* R128PLLWaitForReadUpdateComplete(pScrn);*/ - OUTPLLP(pScrn, R128_PPLL_REF_DIV, - restore->ppll_ref_div, ~R128_PPLL_REF_DIV_MASK); -/* R128PLLWriteUpdate(pScrn); - - R128PLLWaitForReadUpdateComplete(pScrn);*/ - OUTPLLP(pScrn, R128_PPLL_DIV_3, - restore->ppll_div_3, ~R128_PPLL_FB3_DIV_MASK); -/* R128PLLWriteUpdate(pScrn);*/ - OUTPLLP(pScrn, R128_PPLL_DIV_3, - restore->ppll_div_3, ~R128_PPLL_POST3_DIV_MASK); - - R128PLLWriteUpdate(pScrn); - R128PLLWaitForReadUpdateComplete(pScrn); - - OUTPLLP(pScrn, R128_PPLL_DIV_0, - restore->ppll_div_0, ~R128_PPLL_FB0_DIV_MASK); -/* R128PLLWriteUpdate(pScrn);*/ - OUTPLLP(pScrn, R128_PPLL_DIV_0, - restore->ppll_div_0, ~R128_PPLL_POST0_DIV_MASK); - - R128PLLWriteUpdate(pScrn); - R128PLLWaitForReadUpdateComplete(pScrn); - - OUTPLL(R128_HTOTAL_CNTL, restore->htotal_cntl); -/* R128PLLWriteUpdate(pScrn);*/ - - OUTPLLP(pScrn, R128_PPLL_CNTL, 0, ~(R128_PPLL_RESET - | R128_PPLL_SLEEP - | R128_PPLL_ATOMIC_UPDATE_EN - | R128_PPLL_VGA_ATOMIC_UPDATE_EN)); - - R128TRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", - restore->ppll_ref_div, - restore->ppll_div_3, - restore->htotal_cntl, - INPLL(pScrn, R128_PPLL_CNTL))); - R128TRACE(("Wrote: rd=%d, fd=%d, pd=%d\n", - restore->ppll_ref_div & R128_PPLL_REF_DIV_MASK, - restore->ppll_div_3 & R128_PPLL_FB3_DIV_MASK, - (restore->ppll_div_3 & R128_PPLL_POST3_DIV_MASK) >> 16)); - - usleep(5000); /* let the clock lock */ - - OUTPLLP(pScrn, R128_VCLK_ECP_CNTL, - R128_VCLK_SRC_SEL_PPLLCLK, - ~(R128_VCLK_SRC_SEL_MASK)); - -} - /* Write PLL2 registers. */ void R128RestorePLL2Registers(ScrnInfoPtr pScrn, R128SavePtr restore) { -- 2.7.4 _______________________________________________ xorg-driver-ati mailing list xorg-driver-ati@lists.x.org https://lists.x.org/mailman/listinfo/xorg-driver-ati