On Mon, Jun 22, 2009 at 09:56:20PM +0200, Krzysztof Halasa wrote: > My assumption (please correct if wrong): > - it requires interlaced display mode (i830+: practically completed).
sorry, but opposite to i810 and i9xx the i830 is not capable of doing any interlaced video output. > - the video windows must not be scaled vertically. this restriction applies for i810 but is no longer true for i9xx graphics > - sync events for TFF and BFF are signaled by interrupts. For > progressive video (with interlaced display mode, of course) we can not necessarily by driver interrupts. In [1] (intel portion of vga-sync-fields patch) I simply peek some registers (DOVSTA and PIPEA_DSL) directly within the Xserver to determine the actual line + field position of CRT controller at any time. In [2] (radeon portion of the patch) I do the same with radeon graphics. A small DRM-driver patch there is only needed to dynamically alter video output timing. You are right: for i810 some field related overlay regs must be reprogrammed during vertical retrace interrupts. This is no longer true for i9xx architecture. 2 weaved fields are processed there with no driver (interrupt) intervention. - Thomas [1] http://www.easy-vdr.de/git?p=frc.git/.git;a=blob;f=patches/xv-intel.patch;h=b54655a6d6473f55b49fac759f4afc77c101d69f;hb=20810204a85917449096a5fbba65d996c0a1ac2c [2] http://www.easy-vdr.de/git?p=frc.git/.git;a=blob;f=patches/xv-radeon.patch;h=8c6ee3f199f70364c91057c634dfbf864c3db656;hb=20810204a85917449096a5fbba65d996c0a1ac2c _______________________________________________ xorg mailing list xorg@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/xorg