Hi all,
I need recipes for the GTKWAVE, Iverilog, and (Yosys, arachne-pnr, and icebox).
The missing packages are compiled on target P2 B. Plus the recipes that I
already have working below.
These were built on a custom image for the Raspberry Pi 2 B with Yocto.
The following are the recipes that I have created
# meta/recipes-devtools/python/PyPubSub_3.1.3.bb
# meta/recipes-devtools/python/intelhex_1.5.bb
# meta/recipes-devtools/python/python-bitstring_3.1.3.bb
# meta/recipes-devtools/python/pyusb_1.0.0a3.bb
# meta/recipes-devtools/python/rhea_0.1.0.bb
# meta/recipes-devtools/python/xsconnect_0.1.3.bb
# meta/recipes-devtools/python/xstools_0.1.30.bb
Most are the depends are for XSTOOLS. This supports the XuLA2-LX9 & XuLA2-LX25
with StickIt-MB.
http://www.xess.com/ This would be a great addition to the Yocto tools. What
are the steps to add recipes to the Yocto Project? I am using a Fido branch of
Yocto that fetch on 07/20/15.The image is created in 4hrs. on 6 core AMD
running Ubuntu 12.04.
I just completed building the tools (Yosys, arachne-pnr, and icebox) for the
Lattice ICE-40. The complete image fits on a 4GB SD card.
With the board that XESS is making this will be a standalone HDL development
system with GTKWave, XSTOOLs, MyDHDl, Iverilog, arachne-pnr(place and route),
Yosys (Yosys is a framework for Verilog RTL synthesis), icebox(this will not be
needed since XESS is going to push the bit file with GPIO instead of USB), and
MyHDL. These fit on a 4GB SD card.
With the board that XESS is making this will be a standalone HDL development
system with GTKWave, XSTOOLs, MyDHDl, Iverilog, arachne-pnr(place and route),
Yosys (Yosys is a framework for Verilog RTL synthesis), icebox(this will not be
needed since XESS is going to push the bit file with GPIO instead of USB), and
MyHDL.
Dave Vandenbout completed the layout of the ICE-40 board a few days ago.
Lattice iCE40-HX8K FPGA in 256-pin BGA.
32 MByte SDRAM (16M x 16).
Serial configuration flash (at least 2 Mbit).
Three Grove connectors.
Two PMOD connectors.
One 20x2 header with 3.3V, ground and 18 FPGA I/Os.
Two SATA headers (for differential signals; don't know if they would work
with SATA HDDs.)
DIP switch with four SPST switches.
Two momentary pushbuttons.
Four LEDs.
32 KByte HAT EEPROM.
40-pin RPi GPIO header.
Chris Felton provided MyHDL code to take python generates a verilog or VHDL and
the synthesis,
place and route and creates a bin file.
Below are the bench marks for Pi 2B and 2 systems running Ubuntu 12.04.
Yocto Pi 2B
real 0m20.943s
user 0m12.210s
sys 0m0.500s
Ubuntu 2 core
real 0m5.310s
user 0m1.865s
sys 0m0.197s
Ubuntu 6 core
real 0m3.956s
user 0m1.093s
sys 0m0.120s
These were built on a custom image for the Raspberry Pi 2 B with Yocto.
These tools would apply to other boards such a Zynq 7000.
I am also running openCV with 2 C920 cameras.
If you have any questions feel free to contact me.
Edward Vidal Jr. e-mail devel...@sbcglobal.net 915-595-1613
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