This is really a question for the meta-xilinx list but I'll answer it here
anyway.
You need to add the following command (suitably edited) to uEnv.txt on the SD
card:
fatload mmc 0 <memory addr> <bitfile> && fpga loadb 0 <memory addr>
<bitstream size>
<memory addr> is a location in RAM in which the bitstream is temporarily stored
(e.g. 0x100000 but it depends on what else you have in memory)
<bitfile> is the name of the bitstream file (e.g. fpga.bit)
<bitstream size> is the size of the bitstream file.
To get to the U-boot prompt just keep hitting return rapidly during the boot
process. If that works then you can set the countdown to (e.g.) 3 seconds using
the following command:
setenv bootdelay 3
saveenv
This assumes that your version of U-Boot has the FGPA load and boot delay
functionality built in. If not you'll need to rebuild it with the necessary
options enabled.
ALAN LEVY, Lead Consultant, Embedded Systems
Plextek Consulting, The Plextek Building, London Road, Great Chesterford,
Saffron Walden, CB10 1NY, UK
T: +44 (0) 1799 533200 E: alan.l...@plextek.com W: www.plextek.com
>-----Original Message-----
>Date: Tue, 26 Jun 2018 09:05:43 +0000
>From: Simon VII <simon....@outlook.com>
>To: Yocto discussion list <yocto@yoctoproject.org>
>Subject: [yocto] loading FPGA bitfile with u-boot spl on ZYBO
>Message-ID:
>
> <db5pr03mb1765165d1234bb2f642cdf21f2...@db5pr03mb1765.eurprd03.prod.outlook.com>
>
>Content-Type: text/plain; charset="utf-8"
>
>Goodmorning,
>
>
>I hope you can help me with the following matter.
>
>
>I am currently using the poky reference distribution to build a minimal
>working example for the Zybo board (using the meta-xilinx layer), following
>>this<https://www.yoctoproject.org/docs/2.5/brief-yoctoprojectqs/brief-yoctoprojectqs.html>
> guide.
>
>
>After bitbaking the minimal example and putting everything on a partitioned SD
>card, I can start u-boot and load the kernel.
>
>
>Everything seems fine up until here. My problem now is that before loading the
>kernel, I would like to load a bitfile (xxx.bit) and program the FPGA.
>Unfortunatelly I >haven't managed to get this to work.
>
>
>First of all, I am not getting an countdown to interrupt u-boot which I tried
>to identify but was unable to. I am attaching the log from the boot process in
>case it helps. I am >not sure if the u-boot spl is
>
>
>loaded (and executed).
>
<example snipped>
>
>
>I would appreciate any suggestion or help to the right direction.
>
>
>Thanks
>
>Simon
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