Hi
FPGA based DAq for Linux folk --
What your working on seems rather similar to what we are working on...
FPGA controlled Data acquisition and reconfigure able I/O.
The A/Ds we are looking at are 400Khz and / or 2.2Mhz 14 bit converters
See :
14 Bit 400Khz Serial output
http://www.linear.com/cgi-bin/database?function=elementinhtml&filename=DataSheet.html&name=DataSheet&num=588
14 Bit 2.2Mhz Parallel output
http://www.linear.com/cgi-bin/database?function=elementinhtml&filename=DataSheet.html&name=DataSheet&num=515
16 Bit 333 Khz Parallel output
http://www.linear.com/cgi-bin/database?function=elementinhtml&filename=DataSheet.html&name=DataSheet&num=494
The plan is to build them up with a reconfigure able controlled analog sampling
aperture multiplexed front end,
all controlled by way of a smaller Xilinx Vertex download able FPGA also interfaced to
the RT-Linux PCI bus.
The FPGA will also handle Data queuing, front end Mux control, block averaging
and/or digital synchronous demodulation for carrier based
applications. This board will most likely have a number converters, at least two for
simultaneous sampling of Sin / Cos pairs.
This card will most likely also posses optical encoder inputs with 1/T based sub-line
interpolation,
in addition to some form of programmable AC carrier output(s) for sensor excitation.
Like wise we are planing to open the design, but we may try to recoup people's
invested development costs by
giving the first producers of the design a head start to market before making a public
release of the design data bases...
after the head start the FPGA VHDL, Orcad files, BillofMaterials etc. would then go
public.
I do have the Altera and have used them a a few small projects, but I am leaning
towards Xilinks Vertex
for a number of reasons surrounding functional density ( not so much the case for
older XLinks devices )
. Is there a reason why you are going with Altera ?
-Peter
[EMAIL PROTECTED] wrote:
> On Mon, Nov 15, 1999 at 10:43:42PM +0000, John Storrs wrote:
> > Sounds like you might be interested in my fast data acquisition and control
> > project, centred on a generic PCI card design. I'm hoping to have a test card
>
> Sonds like a great card. Two students at NMTech are working on
> a project to use an Altera PCI board with some SRAM, two fat
> FPGAs and a bunch of I/O pins, with RTLinux. We care currently looking
> at communication only, but the plan is to move to DAQ once proof
> of principle is in place.
>
> > PCI development board from PLXTech. The application function in this case is
> > fast data acquisition, with an 80Msps dual channel 8 bit ADC. This can be used
> > for over- or under-sampling (the ADC has a 475MHz sample and hold). The card
> > should provide a good test of the generic design, as well as an interesting
> > application. This is an 'open design' project - I'll be publishing everything
> > (CAD stuff, PLD code, software). More on this later.
>
> Look forward to seeing it.
>
> The big problem with all this is that there is little software for
> generating state machines from Linux. What are you doing to program the PLDs?
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