[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

2024-04-27 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/90187


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[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

2024-04-27 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/90187


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[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

2024-04-27 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/90187


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[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

2024-04-27 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/90187


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[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

2024-04-26 Thread Craig Topper via llvm-branch-commits 

https://github.com/topperc approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/90187
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[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

2024-04-26 Thread Pengcheng Wang via llvm-branch-commits 


@@ -51,6 +51,14 @@ def Feature64Bit
 def FeatureDummy
 : SubtargetFeature<"dummy", "Dummy", "true", "Dummy">;
 
+class RISCVProfile features>
+: SubtargetFeature;
+
+def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>;
+def RVI20U64 : RISCVProfile<"rvi20u64", [Feature64Bit, FeatureStdExtI]>;

wangpc-pp wrote:

We don't handle implications in TableGen, it is in `RISCVISAInfo` where we 
parse the march string. But yeah, I added `F` which implies `Zicsr`.

https://github.com/llvm/llvm-project/pull/90187
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[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

2024-04-26 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/90187


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[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

2024-04-26 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/90187


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[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

2024-04-26 Thread Alex Bradbury via llvm-branch-commits 

https://github.com/asb commented:

Probably best reviewed by someone who has more familiarity with 
RISCVTargetDefEmitter, but I took a look anyway.

I think this direction is OK, though I can't help but feel moving from the ISA 
naming strings to the more verbose listing of features is a bit of a regression 
in terms of ease of reading. I guess we'd be stuck with a recursive dependency 
if we wanted tablegen to be able to parse RISC-V ISA strings, as we'd be 
relying on the tablegenned extension definitions.

https://github.com/llvm/llvm-project/pull/90187
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[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

2024-04-26 Thread Alex Bradbury via llvm-branch-commits 


@@ -51,6 +51,14 @@ def Feature64Bit
 def FeatureDummy
 : SubtargetFeature<"dummy", "Dummy", "true", "Dummy">;
 
+class RISCVProfile features>
+: SubtargetFeature;
+
+def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>;
+def RVI20U64 : RISCVProfile<"rvi20u64", [Feature64Bit, FeatureStdExtI]>;

asb wrote:

It might be worth having a test with at least one extension implication (e.g. 
D, which should pull in F).

https://github.com/llvm/llvm-project/pull/90187
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[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

2024-04-26 Thread Alex Bradbury via llvm-branch-commits 

https://github.com/asb edited https://github.com/llvm/llvm-project/pull/90187
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[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

2024-04-26 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-backend-risc-v

Author: Pengcheng Wang (wangpc-pp)


Changes

So we can only mantain one place.


---
Full diff: https://github.com/llvm/llvm-project/pull/90187.diff


3 Files Affected:

- (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+2-35) 
- (modified) llvm/test/TableGen/riscv-target-def.td (+19) 
- (modified) llvm/utils/TableGen/RISCVTargetDefEmitter.cpp (+29-11) 


``diff
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp 
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index ea0b56b9a1339b..d786f190d9ab6c 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -50,41 +50,8 @@ static const char *RISCVGImplications[] = {
 #define GET_SUPPORTED_EXTENSIONS
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
 
-static constexpr RISCVProfile SupportedProfiles[] = {
-{"rvi20u32", "rv32i"},
-{"rvi20u64", "rv64i"},
-{"rva20u64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_za128rs"},
-{"rva20s64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zifencei_"
- "za128rs_ssccptr_sstvala_sstvecd_svade_svbare"},
-{"rva22u64",
- "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"
- "zicntr_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt"},
-{"rva22s64",
- "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"
- "zicntr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt_ssccptr_"
- "sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"},
-{"rva23u64",
- "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"
- "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_zfa_zfhmin_"
- "zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"},
-{"rva23s64",
- 
"rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"
- "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_"
- "zfa_zfhmin_zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_shcounterenw_"
- "shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_"
- "sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_"
- "svbare_svinval_svnapot_svpbmt"},
-{"rvb23u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"
- "zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_"
- "zimop_za64rs_zawrs_zfa_zcb_zcmop_zba_zbb_zbs_zkt"},
-{"rvb23s64",
- "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"
- "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_"
- 
"zfa_zcb_zcmop_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_sstvala_"
- "sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"},
-{"rvm23u32", "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop_zca_"
- "zcb_zce_zcmop_zcmp_zcmt_zba_zbb_zbs"},
-};
+#define GET_SUPPORTED_PROFILES
+#include "llvm/TargetParser/RISCVTargetParserDef.inc"
 
 static void verifyTables() {
 #ifndef NDEBUG
diff --git a/llvm/test/TableGen/riscv-target-def.td 
b/llvm/test/TableGen/riscv-target-def.td
index 175b68f9f8bad7..afc32086adf99d 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -51,6 +51,14 @@ def Feature64Bit
 def FeatureDummy
 : SubtargetFeature<"dummy", "Dummy", "true", "Dummy">;
 
+class RISCVProfile features>
+: SubtargetFeature;
+
+def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>;
+def RVI20U64 : RISCVProfile<"rvi20u64", [Feature64Bit, FeatureStdExtI]>;
+def ProfileDummy : RISCVProfile<"dummy", [Feature64Bit, FeatureStdExtI, 
FeatureStdExtZidummy]>;
+
 class RISCVProcessorModel f,
@@ -123,6 +131,17 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
 
 // CHECK:  #endif // GET_IMPLIED_EXTENSIONS
 
+// CHECK:  #ifdef GET_SUPPORTED_PROFILES
+// CHECK-NEXT: #undef GET_SUPPORTED_PROFILES
+
+// CHECK:  static constexpr RISCVProfile SupportedProfiles[] = {
+// CHECK-NEXT: {"dummy","rv64i2p1_zidummy0p1"},
+// CHECK-NEXT: {"rvi20u32","rv32i2p1"},
+// CHECK-NEXT: {"rvi20u64","rv64i2p1"},
+// CHECK-NEXT: };
+
+// CHECK:  #endif // GET_SUPPORTED_PROFILES
+
 // CHECK:  #ifndef PROC
 // CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGNED_ACCESS)
 // CHECK-NEXT: #endif
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp 
b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 4580a0ab12669c..8f9a2513184220 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -111,14 +111,14 @@ static void emitRISCVExtensions(RecordKeeper , 
raw_ostream ) {
 //
 // This is almost the same as RISCVFeatures::parseFeatureBits, except that we
 // get feature name from feature records instead of feature bits.
-static void printMArch(raw_ostream , const Record ) {
+static void printMArch(raw_ostream , const std::vector ) 
{
   std::map

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

2024-04-26 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp created 
https://github.com/llvm/llvm-project/pull/90187

So we can only mantain one place.



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