https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/90187
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https://github.com/topperc approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/90187
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@@ -51,6 +51,14 @@ def Feature64Bit
def FeatureDummy
: SubtargetFeature<"dummy", "Dummy", "true", "Dummy">;
+class RISCVProfile features>
+: SubtargetFeature;
+
+def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>;
+def RVI20U64 :
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https://github.com/asb commented:
Probably best reviewed by someone who has more familiarity with
RISCVTargetDefEmitter, but I took a look anyway.
I think this direction is OK, though I can't help but feel moving from the ISA
naming strings to the more verbose listing of features is a bit of
@@ -51,6 +51,14 @@ def Feature64Bit
def FeatureDummy
: SubtargetFeature<"dummy", "Dummy", "true", "Dummy">;
+class RISCVProfile features>
+: SubtargetFeature;
+
+def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>;
+def RVI20U64 :
https://github.com/asb edited https://github.com/llvm/llvm-project/pull/90187
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llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Pengcheng Wang (wangpc-pp)
Changes
So we can only mantain one place.
---
Full diff: https://github.com/llvm/llvm-project/pull/90187.diff
3 Files Affected:
- (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+2-35)
-
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So we can only mantain one place.
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