Hi Julien,
Nice finding :-)
> On 30 Jan 2024, at 18:29, Julien Grall wrote:
>
> From: Julien Grall
>
> Recent rework to the secondary boot code modified how init_ttbr and
> smp_up_cpu are accessed. Rather than directly accessing them, we
> are using a pointer to them.
>
> The helper
flight 184529 xen-4.15-testing real [real]
http://logs.test-lab.xenproject.org/osstest/logs/184529/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-armhf-armhf-libvirt 16 saverestore-support-checkfail like 184107
flight 184533 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/184533/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 909a9a5ae4b8236c1ca7cad7f214c752a579bd67
baseline version:
ovmf
flight 184530 xen-4.16-testing real [real]
flight 184536 xen-4.16-testing real-retest [real]
http://logs.test-lab.xenproject.org/osstest/logs/184530/
http://logs.test-lab.xenproject.org/osstest/logs/184536/
Failures :-/ but no regressions.
Tests which are failing intermittently (not blocking):
flight 184527 xen-unstable real [real]
http://logs.test-lab.xenproject.org/osstest/logs/184527/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-armhf-armhf-libvirt 16 saverestore-support-checkfail like 184518
On 30/01/2024 11:00 pm, Shawn Anastasio wrote:
> Hi Andrew,
>
> On 1/30/24 4:28 PM, Andrew Cooper wrote:
>> All architectures have copy bad logic from x86.
>>
>> OFFSET() having a trailing semi-colon within the macro expansion can be a
>> problematic pattern. It's benign in this case, but fix it
Hi Andrew,
On 1/30/24 4:28 PM, Andrew Cooper wrote:
> All architectures have copy bad logic from x86.
>
> OFFSET() having a trailing semi-colon within the macro expansion can be a
> problematic pattern. It's benign in this case, but fix it anyway.
>
> Perform style fixes for the other macros,
All architectures have copy bad logic from x86.
OFFSET() having a trailing semi-colon within the macro expansion can be a
problematic pattern. It's benign in this case, but fix it anyway.
Perform style fixes for the other macros, and tame the mess of BLANK()
position to be consistent (one
All these cases happen to be benign, but drop them anyway. This is one step
towards making -Wextra-semi work.
Signed-off-by: Andrew Cooper
---
CC: George Dunlap
CC: Jan Beulich
CC: Stefano Stabellini
CC: Wei Liu
CC: Julien Grall
---
xen/common/sched/private.h | 2 +-
Tamas reported this UBSAN failure from fuzzing:
(XEN)
(XEN) UBSAN: Undefined behaviour in common/sched/compat.c:48:37
(XEN) left shift of negative value -2147425536
(XEN) [ Xen-4.19-unstable x86_64
On Tue, Jan 30, 2024 at 10:07:36AM +0100, Roger Pau Monné wrote:
> On Mon, Jan 29, 2024 at 04:01:13PM -0600, Bjorn Helgaas wrote:
> > On Thu, Jan 25, 2024 at 07:17:24AM +, Chen, Jiqian wrote:
> > > On 2024/1/24 00:02, Bjorn Helgaas wrote:
> > > > On Tue, Jan 23, 2024 at 10:13:52AM +, Chen,
flight 184526 libvirt real [real]
http://logs.test-lab.xenproject.org/osstest/logs/184526/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-armhf-armhf-libvirt 16 saverestore-support-checkfail like 184488
test-armhf-armhf-libvirt-qcow2 15
On 1/9/24 16:51, Stewart Hildebrand wrote:
> diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c
> index 3a973324bca1..a902de6a8693 100644
> --- a/xen/drivers/passthrough/pci.c
> +++ b/xen/drivers/passthrough/pci.c
> @@ -1476,6 +1485,10 @@ static int assign_device(struct
Tamas reported this UBSAN failure from fuzzing:
(XEN)
(XEN) UBSAN: Undefined behaviour in common/vsprintf.c:64:19
(XEN) negation of -9223372036854775808 cannot be represented in type 'long
long int':
(XEN)
On 30.01.24 19:29, Julien Grall wrote:
Hello Julien
> From: Julien Grall
>
> Recent rework to the secondary boot code modified how init_ttbr and
> smp_up_cpu are accessed. Rather than directly accessing them, we
> are using a pointer to them.
>
> The helper clean_dcache() is expected to
flight 184525 linux-linus real [real]
http://logs.test-lab.xenproject.org/osstest/logs/184525/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stopfail like 184517
test-amd64-amd64-xl-qemuu-win7-amd64
From: Julien Grall
Recent rework to the secondary boot code modified how init_ttbr and
smp_up_cpu are accessed. Rather than directly accessing them, we
are using a pointer to them.
The helper clean_dcache() is expected to take the variable in parameter
and then clean its content. As we now pass
On Tue, Jan 30, 2024 at 04:25:40PM +, Andrew Cooper wrote:
> On 30/01/2024 9:13 am, Roger Pau Monne wrote:
> > Roger Pau Monne (3):
> > x86/intel: expose IPRED_CTRL to guests
> > x86/intel: expose RRSBA_CTRL to guests
> > x86/intel: expose BHI_CTRL to guests
>
> A couple of things.
On Mon, Jan 29, 2024 at 05:44:43PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Mon, 29 Jan 2024 17:44:43 +0100
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 01/29] bulk: Access existing variables initialized to
> >F when available
> X-Mailer: git-send-email 2.41.0
>
> When a variable is
flight 184528 xen-unstable-smoke real [real]
http://logs.test-lab.xenproject.org/osstest/logs/184528/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-libvirt 15 migrate-support-checkfail never pass
test-arm64-arm64-xl-xsm
On 30/01/2024 9:13 am, Roger Pau Monne wrote:
> Roger Pau Monne (3):
> x86/intel: expose IPRED_CTRL to guests
> x86/intel: expose RRSBA_CTRL to guests
> x86/intel: expose BHI_CTRL to guests
A couple of things. First,
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index
On Mon, Jan 29, 2024 at 05:44:56PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Mon, 29 Jan 2024 17:44:56 +0100
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 14/29] target/i386: Prefer fast cpu_env() over slower
> CPU QOM cast macro
> X-Mailer: git-send-email 2.41.0
>
> Mechanical patch
On 30/01/2024 12:59 pm, Jan Beulich wrote:
> On 30.01.2024 13:06, Roger Pau Monné wrote:
>> On Tue, Jan 30, 2024 at 11:57:17AM +0100, Jan Beulich wrote:
>>> On 30.01.2024 10:13, Roger Pau Monne wrote:
The CPUID feature bit signals the presence of the IPRED_DIS_{U,S} controls
in
Hello all,
The official project git repositories on https://xenbits.xen.org/ do not
let people subscribe to get eg. notifications on push. A few repos are
mirrored in https://gitlab.com/xen-project/ but it does not look like
there are that many of them, aside from xen.git.
I would love to
On Tue, 2024-01-30 at 16:05 +0100, Jan Beulich wrote:
> On 30.01.2024 15:57, Oleksii wrote:
> > On Mon, 2024-01-22 at 17:27 +0100, Jan Beulich wrote:
> > > > +#define __xchg_acquire(ptr, new, size) \
> > > > +({ \
> > > > + __typeof__(ptr) ptr__ = (ptr); \
> > > > + __typeof__(new) new__ =
On 30.01.2024 16:08, Andrew Cooper wrote:
> ... as with other declarations which aren't legal to call from C.
>
> Signed-off-by: Andrew Cooper
Acked-by: Jan Beulich
On 30.01.2024 15:48, Andrew Cooper wrote:
> 107 lines is an unreasonably large switch statement to live inside a
> brace-less for loop. Drop the comment that's clumsily trying to cover the
> fact that this logic has wrong-looking indentation.
>
> No functional change.
>
> Signed-off-by: Andrew
... as with other declarations which aren't legal to call from C.
Signed-off-by: Andrew Cooper
---
CC: Jan Beulich
CC: Roger Pau Monné
CC: Wei Liu
---
xen/arch/x86/x86_64/traps.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/x86_64/traps.c
On 30.01.2024 15:57, Oleksii wrote:
> On Mon, 2024-01-22 at 17:27 +0100, Jan Beulich wrote:
>>> +#define __xchg_acquire(ptr, new, size) \
>>> +({ \
>>> + __typeof__(ptr) ptr__ = (ptr); \
>>> + __typeof__(new) new__ = (new); \
>>> + __typeof__(*(ptr)) ret__; \
>>> + switch (size) \
>>>
On 1/25/24 07:33, Roger Pau Monné wrote:
> On Thu, Jan 25, 2024 at 12:23:05PM +0100, Jan Beulich wrote:
>> On 25.01.2024 10:05, Roger Pau Monné wrote:
>>> On Thu, Jan 25, 2024 at 08:43:05AM +0100, Jan Beulich wrote:
On 24.01.2024 18:51, Roger Pau Monné wrote:
> On Wed, Jan 24, 2024 at
On 30/01/2024 3:02 pm, Roger Pau Monné wrote:
> On Tue, Jan 30, 2024 at 01:55:56PM +0100, Jan Beulich wrote:
>> On 30.01.2024 12:46, Roger Pau Monné wrote:
>>> On Tue, Jan 30, 2024 at 11:42:43AM +0100, Jan Beulich wrote:
On 30.01.2024 11:27, Roger Pau Monne wrote:
> Dummy set/clear tests
On Tue, Jan 30, 2024 at 01:55:56PM +0100, Jan Beulich wrote:
> On 30.01.2024 12:46, Roger Pau Monné wrote:
> > On Tue, Jan 30, 2024 at 11:42:43AM +0100, Jan Beulich wrote:
> >> On 30.01.2024 11:27, Roger Pau Monne wrote:
> >>> Dummy set/clear tests for additional spec_ctrl bits.
> >>> ---
> >>>
On Tue, Jan 30, 2024 at 03:47:37PM +0100, Jan Beulich wrote:
> On 30.01.2024 15:35, Roger Pau Monné wrote:
> > On Tue, Jan 30, 2024 at 01:59:14PM +0100, Jan Beulich wrote:
> >> On 30.01.2024 13:06, Roger Pau Monné wrote:
> >>> On Tue, Jan 30, 2024 at 11:57:17AM +0100, Jan Beulich wrote:
> On
On 1/24/24 00:00, Stewart Hildebrand wrote:
> On 1/23/24 10:07, Roger Pau Monné wrote:
>> On Tue, Jan 23, 2024 at 03:32:12PM +0100, Jan Beulich wrote:
>>> On 15.01.2024 20:43, Stewart Hildebrand wrote:
@@ -2888,6 +2888,8 @@ int allocate_and_map_msi_pirq(struct domain *d, int
index, int
On Mon, 2024-01-22 at 17:27 +0100, Jan Beulich wrote:
> > +#define __xchg_acquire(ptr, new, size) \
> > +({ \
> > + __typeof__(ptr) ptr__ = (ptr); \
> > + __typeof__(new) new__ = (new); \
> > + __typeof__(*(ptr)) ret__; \
> > + switch (size) \
> > + { \
> > + case 4: \
> > +
Hi all,
Please add your proposed agenda items below.
https://cryptpad.fr/pad/#/2/pad/edit/mc3pbD9Wghw16Gq1MGyn7mbe/
If any action items are missing or have been resolved, please add/remove
them from the sheet.
*CALL LINK: https://meet.jit.si/XenProjectCommunityCall
107 lines is an unreasonably large switch statement to live inside a
brace-less for loop. Drop the comment that's clumsily trying to cover the
fact that this logic has wrong-looking indentation.
No functional change.
Signed-off-by: Andrew Cooper
---
CC: Jan Beulich
CC: Roger Pau Monné
CC:
On 30.01.2024 15:35, Roger Pau Monné wrote:
> On Tue, Jan 30, 2024 at 01:59:14PM +0100, Jan Beulich wrote:
>> On 30.01.2024 13:06, Roger Pau Monné wrote:
>>> On Tue, Jan 30, 2024 at 11:57:17AM +0100, Jan Beulich wrote:
On 30.01.2024 10:13, Roger Pau Monne wrote:
> The CPUID feature bit
On Tue, Jan 30, 2024 at 01:59:14PM +0100, Jan Beulich wrote:
> On 30.01.2024 13:06, Roger Pau Monné wrote:
> > On Tue, Jan 30, 2024 at 11:57:17AM +0100, Jan Beulich wrote:
> >> On 30.01.2024 10:13, Roger Pau Monne wrote:
> >>> The CPUID feature bit signals the presence of the IPRED_DIS_{U,S}
>
A new pre-release of our guest agent prototype written in Rust is
available, numbered 0.3.0 [1]. Identified issues and work to be done
are tracked in Gitlab issue tracker [2].
As always, feedback will be greatly appreciated!
Highlights:
### new features
* can be linked statically with
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Xen Security Advisory CVE-2023-46839 / XSA-449
version 2
pci: phantom functions assigned to incorrect contexts
UPDATES IN VERSION 2
Public release.
ISSUE DESCRIPTION
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Xen Security Advisory CVE-2023-46840 / XSA-450
version 2
VT-d: Failure to quarantine devices in !HVM builds
UPDATES IN VERSION 2
Public release.
ISSUE DESCRIPTION
On Mon, 29 Jan 2024 17:44:56 +0100
Philippe Mathieu-Daudé wrote:
> Mechanical patch produced running the command documented
> in scripts/coccinelle/cpu_env.cocci_template header.
commenting here since, I'm not expert on coccinelle scripts.
On negative side we are permanently loosing type
On 30.01.2024 13:06, Roger Pau Monné wrote:
> On Tue, Jan 30, 2024 at 11:57:17AM +0100, Jan Beulich wrote:
>> On 30.01.2024 10:13, Roger Pau Monne wrote:
>>> The CPUID feature bit signals the presence of the IPRED_DIS_{U,S} controls
>>> in
>>> SPEC_CTRL MSR.
>>>
>>> Note that those controls are
flight 184523 linux-5.4 real [real]
http://logs.test-lab.xenproject.org/osstest/logs/184523/
Failures :-/ but no regressions.
Tests which are failing intermittently (not blocking):
test-armhf-armhf-xl-credit1 8 xen-boot fail in 184507 pass in 184523
test-armhf-armhf-xl-rtds 14
On 30.01.2024 12:46, Roger Pau Monné wrote:
> On Tue, Jan 30, 2024 at 11:42:43AM +0100, Jan Beulich wrote:
>> On 30.01.2024 11:27, Roger Pau Monne wrote:
>>> Dummy set/clear tests for additional spec_ctrl bits.
>>> ---
>>> docs/all-tests.dox | 2 +
>>> tests/test/Makefile | 9
>>>
On Tue, Jan 30, 2024 at 11:57:17AM +0100, Jan Beulich wrote:
> On 30.01.2024 10:13, Roger Pau Monne wrote:
> > The CPUID feature bit signals the presence of the IPRED_DIS_{U,S} controls
> > in
> > SPEC_CTRL MSR.
> >
> > Note that those controls are not used by the hypervisor.
>
> Despite this,
On Tue, Jan 30, 2024 at 11:42:43AM +0100, Jan Beulich wrote:
> On 30.01.2024 11:27, Roger Pau Monne wrote:
> > Dummy set/clear tests for additional spec_ctrl bits.
> > ---
> > docs/all-tests.dox | 2 +
> > tests/test/Makefile | 9
> > tests/test/main.c | 100
On 30.01.2024 10:13, Roger Pau Monne wrote:
> The CPUID feature bit signals the presence of the IPRED_DIS_{U,S} controls in
> SPEC_CTRL MSR.
>
> Note that those controls are not used by the hypervisor.
Despite this, ...
> --- a/xen/arch/x86/msr.c
> +++ b/xen/arch/x86/msr.c
> @@ -324,6 +324,9 @@
On 30.01.2024 11:27, Roger Pau Monne wrote:
> Dummy set/clear tests for additional spec_ctrl bits.
> ---
> docs/all-tests.dox | 2 +
> tests/test/Makefile | 9
> tests/test/main.c | 100
> 3 files changed, 111 insertions(+)
> create mode
Dummy set/clear tests for additional spec_ctrl bits.
---
docs/all-tests.dox | 2 +
tests/test/Makefile | 9
tests/test/main.c | 100
3 files changed, 111 insertions(+)
create mode 100644 tests/test/Makefile
create mode 100644
Manos Pitsidianakis writes:
> According to the QEMU Coding Style document:
>
>> Do not use printf(), fprintf() or monitor_printf(). Instead, use
>> error_report() or error_vreport() from error-report.h. This ensures the
>> error is reported in the right place (current monitor or stderr), and in
Manos Pitsidianakis writes:
> Tracing DPRINTFs to stderr might not be desired. A developer that relies
> on tracepoints should be able to opt-in to each tracepoint and rely on
> QEMU's log redirection, instead of stderr by default.
>
> This commit converts DPRINTFs in this file that are used for
Manos Pitsidianakis writes:
> Tracing DPRINTFs to stderr might not be desired. A developer that relies
> on tracepoints should be able to opt-in to each tracepoint and rely on
> QEMU's log redirection, instead of stderr by default.
>
> This commit converts DPRINTFs in this file that are used for
On 25.01.2024 19:14, Jason Andryuk wrote:
> xenpm get-cpufreq-states currently just prints no output when cpufreq is
> disabled or HWP is running. Have it print an appropriate message. The
> cpufreq disabled one mirrors the cpuidle disabled one.
>
> cpufreq disabled:
> $ xenpm
On 26.01.2024 21:54, Andrew Cooper wrote:
> In 13y of working on Xen, I've never seen seen it used. The implementation
> was introduced (commit b69f92f3012e, Jul 28 2004) with known issues such as:
>
> /* Resuming after we've stopped used to work, but more through luck
> than any actual
On 26.01.2024 21:54, Andrew Cooper wrote:
> --- a/xen/arch/x86/include/asm/bug.h
> +++ b/xen/arch/x86/include/asm/bug.h
> @@ -1,28 +1,8 @@
> #ifndef __X86_BUG_H__
> #define __X86_BUG_H__
>
> -/*
> - * Please do not include in the header any header that might
> - * use BUG/ASSERT/etc maros
Hello,
Introduce support for exposing {IPRED,RRSBA,BHI}_CTRL feature bits and
allow setting the corresponding SPEC_CTRL MSR fields.
The bits are documented in:
The CPUID feature bit signals the presence of the IPRED_DIS_{U,S} controls in
SPEC_CTRL MSR.
Note that those controls are not used by the hypervisor.
Signed-off-by: Roger Pau Monné
---
xen/arch/x86/msr.c | 3 +++
xen/include/public/arch-x86/cpufeatureset.h | 2 +-
The CPUID feature bit signals the presence of the BHI_DIS_S control in
SPEC_CTRL MSR.
Note that those controls are not used by the hypervisor.
Signed-off-by: Roger Pau Monné
---
xen/arch/x86/msr.c | 1 +
xen/include/public/arch-x86/cpufeatureset.h | 2 +-
The CPUID feature bit signals the presence of the RRSBA_DIS_{U,S} controls in
SPEC_CTRL MSR.
Note that those controls are not used by the hypervisor.
Signed-off-by: Roger Pau Monné
---
xen/arch/x86/msr.c | 3 +++
xen/include/public/arch-x86/cpufeatureset.h | 2 +-
Hi Carlo,
On 29/01/2024 18:17, Carlo Nonato wrote:
>
>
> Shared caches in multi-core CPU architectures represent a problem for
> predictability of memory access latency. This jeopardizes applicability
> of many Arm platform in real-time critical and mixed-criticality
> scenarios. We introduce
On 30.01.2024 10:01, GitLab wrote:
>
>
> Pipeline #1155726092 has failed!
>
> Project: xen ( https://gitlab.com/xen-project/xen )
> Branch: staging ( https://gitlab.com/xen-project/xen/-/commits/staging )
>
> Commit: 40a74677 (
>
On Mon, Jan 29, 2024 at 04:01:13PM -0600, Bjorn Helgaas wrote:
> On Thu, Jan 25, 2024 at 07:17:24AM +, Chen, Jiqian wrote:
> > On 2024/1/24 00:02, Bjorn Helgaas wrote:
> > > On Tue, Jan 23, 2024 at 10:13:52AM +, Chen, Jiqian wrote:
> > >> On 2024/1/23 07:37, Bjorn Helgaas wrote:
> > >>> On
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