http://bugzilla.kernel.org/show_bug.cgi?id=11541





------- Comment #60 from v.ples...@gmail.com  2009-01-21 09:23 -------

Regarding MTRR:

Memory Type Range Registers
http://en.wikipedia.org/wiki/Mtrr

Memory Type Range Registers (MTRRs) are a set of Processor Supplementary
Capabilities control registers that provide system software with control of how
accesses to memory ranges by the CPU are cached. It uses a set of programmable
model-specific registers (MSRs) which are special registers provided by most
modern CPUs.

Possible access modes to memory ranges can be:
    * uncached
    * write-through
    * write-combining
    * write-protect
    * write-back
. . .

Successor

Newer (primarily 64-bit) x86 CPU's support a more advanced technique called
Page Attribute Tables that allow for per-table setting of these modes, instead
of having a limited number of low-granularity registers to deal with modern
memory sizes that can be as high as 8GB even on a laptop, and several times
that amount on a desktop system.

Details on how MTRRs work in detail are described in the processor manuals from
CPU vendors.

http://en.wikipedia.org/wiki/Page_Attribute_Table

The Page Attribute Table (also known as Page Allocation Table) is a Processor
Supplementary Capability extension to the page table format of certain x86 and
x86-64 microprocessors. Like Memory Type Range Registers (MTRRs), they allow
for fine-grained control over how areas of memory are cached.

Unlike MTRRs, which provide the ability to manipulate the behavior of caching
for a limited number of fixed physical address ranges, Page Attribute Tables
allow for such behavior to be specified on a per-page basis, greatly increasing
the ability of the operating system to select the most efficient behavior for
any given task.


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