Thats right. Clock speed is governed by slowest processing stage + register
delay. With clock cycle of  (160+5) ns even the faster stages will be forced
to run slowly. As a result 1st instruction will take 165*4 ns and rest of
following 999 instructions will take 165*999 ns.

On Tue, Sep 27, 2011 at 4:03 PM, praneethn <praneeth...@gmail.com> wrote:

>
> clock period=(slowest stage delay)+(Buffer delay).
>
> slowest stage delay is 160 ns and Buffer delay is 5ns. Buffer delay will
> always be there between two stages .
>
> clock period=165ns.
>
> In the pipelining the time it takes =(k+n-1) * (clock period)
>
> k=number of stages and n=number of instructions(data items)
>
> hence time it takes=(4+1000-1)*(165)=165.4 microsec
>
>
>
>
> On Tue, Sep 27, 2011 at 11:51 AM, Aditya Virmani <virmanisadi...@gmail.com
> > wrote:
>
>> 585 + (160 + 5)for slowest transactions *999 for the rest of the
>> instructions!
>>
>>
>> On Tue, Sep 27, 2011 at 12:49 AM, Gene <gene.ress...@gmail.com> wrote:
>>
>>> You guys have the right idea except that since it's multiple choice
>>> you can do this with no math.  With 1000 data items and only 4 stages,
>>> the bottleneck has to be the slowest pipeline stage with its register
>>> delay.  So you can answer b in 10 seconds and move on to the next
>>> question!
>>>
>>> On Sep 26, 8:50 pm, Dumanshu <duman...@gmail.com> wrote:
>>> > @bharat:
>>> > for the second part where u multiplied (160+5) with 999, it should be
>>> > 160*999 because it is max of (150,120,160,140,5). Correct me if i am
>>> > wrong.
>>> >
>>> > On Sep 26, 4:02 pm, bharatkumar bagana <bagana.bharatku...@gmail.com>
>>> > wrote:
>>> >
>>> >
>>> >
>>> > > for the first instruction : 150+5+120+5+160+5+140=585 ns
>>> > > for the rest of the instructions , though pipeline----
>>> > > max(150,120,160,140)=160
>>> >
>>> > > (160+5)*999=164835 ns
>>> > >  we assume that there will be no extra stalls existed in our system
>>> > > ---------585 + 164835 =165420 ns =165.4 us...
>>> > > correct me if I'm wrong .........
>>> >
>>> > > On Sun, Sep 25, 2011 at 9:25 AM, siva viknesh <
>>> sivavikne...@gmail.com>wrote:
>>> >
>>> > > > A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 ns
>>> > > > (nano seconds)
>>> > > > respectively. Registers that are used between the stages have a
>>> delay
>>> > > > of 5 ns each. Assuming
>>> > > > constant clocking rate, the total time taken to process 1000 data
>>> > > > items on this pipeline will
>>> > > > approximately be
>>> > > > a. 120 us (micro seconds)
>>> > > > b. 165 us
>>> > > > c. 180 us
>>> > > > d. 175 us
>>> >
>>> > > > ...plz give detailed explanation for the ans
>>> >
>>> > > > --
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>>> > > --
>>> >
>>> > > **Regards
>>> > > *BharatKumar Bagana*
>>> > > **http://www.google.com/profiles/bagana.bharatkumar<
>>> http://www.google.com/profiles/bagana.bharatkumar>
>>> > > *
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