Update of /cvsroot/alsa/alsa-kernel/pci/cs46xx
In directory sc8-pr-cvs1:/tmp/cvs-serv10706
Modified Files:
cs46xx_lib.c cs46xx_lib.h dsp_spos.c dsp_spos_scb_lib.c
Log Message:
updates by Benny Sjostrand:
- Added the cwcdma DSP firmware module
- Fixed a minor bug in cs46xx_iec958_pre_open(...)
- in cs46xx_dsp_enable_spdif_hw(...), disable SPDIF hw
before enabling, this seems to help solving the synchronization issue
- Some changes in cs46xx_dsp_create_pcm_channel(...) and
cs46xx_dsp_create_src_task_scb(...) to adapt to the new DSP firmware.
Index: cs46xx_lib.c
===================================================================
RCS file: /cvsroot/alsa/alsa-kernel/pci/cs46xx/cs46xx_lib.c,v
retrieving revision 1.51
retrieving revision 1.52
diff -u -r1.51 -r1.52
--- cs46xx_lib.c 28 Feb 2003 16:30:14 -0000 1.51
+++ cs46xx_lib.c 3 Mar 2003 11:33:00 -0000 1.52
@@ -321,6 +321,7 @@
#include "imgs/cwcasync.h"
#include "imgs/cwcsnoop.h"
#include "imgs/cwcbinhack.h"
+#include "imgs/cwcdma.h"
int snd_cs46xx_clear_BA1(cs46xx_t *chip,
unsigned long offset,
@@ -3165,6 +3166,11 @@
if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) {
snd_printk(KERN_ERR "image download error [cwcbinhack]\n");
+ return -EIO;
+ }
+
+ if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) {
+ snd_printk(KERN_ERR "image download error [cwcdma]\n");
return -EIO;
}
Index: cs46xx_lib.h
===================================================================
RCS file: /cvsroot/alsa/alsa-kernel/pci/cs46xx/cs46xx_lib.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -r1.10 -r1.11
--- cs46xx_lib.h 9 Dec 2002 11:26:07 -0000 1.10
+++ cs46xx_lib.h 3 Mar 2003 11:33:01 -0000 1.11
@@ -156,7 +156,8 @@
u16 src_buffer_addr,
u16 src_delay_buffer_addr,u32
dest,
dsp_scb_descriptor_t *
parent_scb,
- int scb_child_type);
+ int scb_child_type,
+ int pass_through);
dsp_scb_descriptor_t * cs46xx_dsp_create_mix_only_scb(cs46xx_t * chip,char *
scb_name,
u16 mix_buffer_addr,u32 dest,
dsp_scb_descriptor_t *
parent_scb,
Index: dsp_spos.c
===================================================================
RCS file: /cvsroot/alsa/alsa-kernel/pci/cs46xx/dsp_spos.c,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -r1.18 -r1.19
--- dsp_spos.c 6 Feb 2003 16:17:34 -0000 1.18
+++ dsp_spos.c 3 Mar 2003 11:33:01 -0000 1.19
@@ -1371,11 +1371,11 @@
/* SPDIF input sampel rate converter */
src_task_scb = cs46xx_dsp_create_src_task_scb(chip,"SrcTaskSCB_SPDIFI",
- 48000,
+ ins->spdif_in_sample_rate,
SRC_OUTPUT_BUF1,
SRC_DELAY_BUF1,SRCTASK_SCB_ADDR,
master_mix_scb,
- SCB_ON_PARENT_SUBLIST_SCB);
+ SCB_ON_PARENT_SUBLIST_SCB,0);
if (!src_task_scb) goto _fail_end;
@@ -1564,9 +1564,32 @@
return 0;
}
+
+static void cs46xx_dsp_disable_spdif_hw (cs46xx_t *chip)
+{
+ dsp_spos_instance_t * ins = chip->dsp_spos_instance;
+
+ /* set SPDIF output FIFO slot */
+ snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, 0);
+
+ /* SPDIF output MASTER ENABLE */
+ cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0);
+
+ /* right and left validate bit */
+ /*cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);*/
+ cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, 0x0);
+
+ /* monitor state */
+ ins->spdif_status_out &= ~DSP_SPDIF_STATUS_HW_ENABLED;
+}
+
int cs46xx_dsp_enable_spdif_hw (cs46xx_t *chip)
{
dsp_spos_instance_t * ins = chip->dsp_spos_instance;
+
+ /* if hw-ctrl already enabled, turn off to reset logic ... */
+ cs46xx_dsp_disable_spdif_hw (chip);
+ udelay(50);
/* set SPDIF output FIFO slot */
snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, ( 0x8000 | ((SP_SPDOUT_FIFO >> 4) <<
4) ));
Index: dsp_spos_scb_lib.c
===================================================================
RCS file: /cvsroot/alsa/alsa-kernel/pci/cs46xx/dsp_spos_scb_lib.c,v
retrieving revision 1.19
retrieving revision 1.20
diff -u -r1.19 -r1.20
--- dsp_spos_scb_lib.c 26 Feb 2003 08:45:58 -0000 1.19
+++ dsp_spos_scb_lib.c 3 Mar 2003 11:33:01 -0000 1.20
@@ -584,7 +584,8 @@
u16 src_buffer_addr,
u16 src_delay_buffer_addr,u32 dest,
dsp_scb_descriptor_t * parent_scb,
- int scb_child_type)
+ int scb_child_type,
+ int pass_through)
{
dsp_spos_instance_t * ins = chip->dsp_spos_instance;
@@ -659,10 +660,22 @@
/* clear buffers */
_dsp_clear_sample_buffer (chip,src_buffer_addr,8);
_dsp_clear_sample_buffer (chip,src_delay_buffer_addr,32);
-
- scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
- dest,ins->s16_up,parent_scb,
- scb_child_type);
+
+ if (pass_through) {
+ /* wont work with any other rate than
+ the native DSP rate */
+ snd_assert (rate = 48000);
+
+ scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32
*)&src_task_scb,
+
dest,"DMAREADER",parent_scb,
+ scb_child_type);
+ } else {
+ scb = _dsp_create_generic_scb(chip,scb_name,(u32
*)&src_task_scb,
+ dest,ins->s16_up,parent_scb,
+ scb_child_type);
+ }
+
+
}
return scb;
@@ -835,10 +848,10 @@
RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_16,
0,
- 0,input_scb->address,
+ /* 0xD */ 0,input_scb->address,
{
- 0x8000,0x8000,
- 0x8000,0x8000
+ /* 0xE */ 0x8000,0x8000,
+ /* 0xF */ 0x8000,0x8000
}
};
@@ -1134,9 +1147,9 @@
dsp_scb_descriptor_t * src_scb = NULL,* pcm_scb, * mixer_scb = NULL;
dsp_scb_descriptor_t * src_parent_scb = NULL;
- /*dsp_scb_descriptor_t * pcm_parent_scb;*/
+ /* dsp_scb_descriptor_t * pcm_parent_scb; */
char scb_name[DSP_MAX_SCB_NAME];
- int i,pcm_index = -1, insert_point, src_index = -1;
+ int i,pcm_index = -1, insert_point, src_index = -1,pass_through = 0;
unsigned long flags;
switch (pcm_channel_id) {
@@ -1163,7 +1176,8 @@
alter the raw data stream ...) */
if (sample_rate == 48000) {
snd_printdd ("IEC958 pass through\n");
- src_parent_scb = ins->asynch_tx_scb;
+ /* Hack to bypass creating a new SRC */
+ pass_through = 1;
}
break;
default:
@@ -1216,18 +1230,16 @@
snd_assert (src_index != -1,return NULL);
/* we need to create a new SRC SCB */
- if (src_parent_scb == NULL) {
- if (mixer_scb->sub_list_ptr == ins->the_null_scb) {
- src_parent_scb = mixer_scb;
- insert_point = SCB_ON_PARENT_SUBLIST_SCB;
- } else {
- src_parent_scb =
find_next_free_scb(chip,mixer_scb->sub_list_ptr);
- insert_point = SCB_ON_PARENT_NEXT_SCB;
- }
- } else insert_point = SCB_ON_PARENT_NEXT_SCB;
+ if (mixer_scb->sub_list_ptr == ins->the_null_scb) {
+ src_parent_scb = mixer_scb;
+ insert_point = SCB_ON_PARENT_SUBLIST_SCB;
+ } else {
+ src_parent_scb =
find_next_free_scb(chip,mixer_scb->sub_list_ptr);
+ insert_point = SCB_ON_PARENT_NEXT_SCB;
+ }
snprintf (scb_name,DSP_MAX_SCB_NAME,"SrcTask_SCB%d",src_index);
-
+
snd_printdd( "dsp_spos: creating SRC \"%s\"\n",scb_name);
src_scb = cs46xx_dsp_create_src_task_scb(chip,scb_name,
sample_rate,
@@ -1236,7 +1248,8 @@
/* 0x400 - 0x600 source SCBs
*/
0x400 + (src_index * 0x10) ,
src_parent_scb,
- insert_point);
+ insert_point,
+ pass_through);
if (!src_scb) {
snd_printk (KERN_ERR "dsp_spos: failed to create
SRCtaskSCB\n");
@@ -1268,19 +1281,6 @@
snd_printk (KERN_ERR "dsp_spos: failed to create PCMreaderSCB\n");
return NULL;
}
-
- if (pcm_channel_id == DSP_IEC958_CHANNEL && sample_rate == 48000) {
- snd_assert (ins->spdif_pcm_input_scb == NULL);
-
- /* a hack to make the skip the SRC and pass the stream
- directly to the SPDIF task */
- ins->spdif_pcm_input_scb =
-
cs46xx_dsp_create_pcm_serial_input_scb(chip,"PCMSerialInput_PCM",
- PCMSERIALINII_SCB_ADDR,
- pcm_scb,
- ins->asynch_tx_scb,
-
SCB_ON_PARENT_SUBLIST_SCB);
- }
spin_lock_irqsave(&chip->reg_lock, flags);
ins->pcm_channels[pcm_index].sample_rate = sample_rate;
@@ -1625,7 +1625,7 @@
}
/* if not enabled already */
- if (ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) {
+ if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
cs46xx_dsp_enable_spdif_hw (chip);
}
@@ -1669,7 +1669,6 @@
_dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
/* restore state */
-
if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
cs46xx_dsp_enable_spdif_out (chip);
}
-------------------------------------------------------
This sf.net email is sponsored by:ThinkGeek
Welcome to geek heaven.
http://thinkgeek.com/sf
_______________________________________________
Alsa-cvslog mailing list
[EMAIL PROTECTED]
https://lists.sourceforge.net/lists/listinfo/alsa-cvslog
