Update of /cvsroot/alsa/alsa-kernel/pci/cs46xx/imgs
In directory sc8-pr-cvs1:/tmp/cvs-serv15194
Added Files:
cwcdma.asp cwcdma.h
Log Message:
updates by Benny:
- Added the cwcdma DSP firmware module
- Fixed a minor bug in cs46xx_iec958_pre_open(...)
- in cs46xx_dsp_enable_spdif_hw(...), disable SPDIF hw
before enabling, this seems to help solving the synchronization issue
- Some changes in cs46xx_dsp_create_pcm_channel(...) and
cs46xx_dsp_create_src_task_scb(...) to adapt to the new DSP firmware.
--- NEW FILE: cwcdma.asp ---
//
// Copyright(c) by Benny Sjostrand ([EMAIL PROTECTED])
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
//
// This code runs inside the DSP (cs4610, cs4612, cs4624, or cs4630),
// to compile it you need a tool named SPASM 3.0 and DSP code owned by
// Cirrus Logic(R). The SPASM program will generate a object file (cwcdma.osp),
// the "ospparser" tool will genereate the cwcdma.h file it's included from
// the cs46xx_lib.c file.
//
//
// The purpose of this code is very simple: make it possible to tranfser
// the samples 'as they are' with no alteration from a PCMreader SCB (DMA from host)
// to any other SCB. This is useful for AC3 throug SPDIF. SRC (source rate converters)
// task always alters the samples in some how, however it's from 48khz -> 48khz. The
// alterations are not audible, but AC3 wont work.
//
// ...
// |
// +---------------+
// | AsynchFGTxSCB |
// +---------------+
// |
// subListPtr
// |
// +--------------+
// | DMAReader |
// +--------------+
// |
// subListPtr
// |
// +-------------+
// | PCMReader |
// +-------------+
// (DMA from host)
//
struct dmaSCB
{
long dma_reserved1[3];
short dma_reserved2:dma_outBufPtr;
short dma_unused1:dma_unused2;
long dma_reserved3[4];
short dma_subListPtr:dma_nextSCB;
short dma_SPBptr:dma_entryPoint;
long dma_strmRsConfig;
long dma_strmBufPtr;
long dma_reserved4;
VolumeControl s2m_volume;
};
#export DMAReader
void DMAReader()
{
execChild();
r2 = r0->dma_subListPtr;
r1 = r0->nextSCB;
rsConfig01 = r2->strmRsConfig;
// Load rsConfig for input buffer
rsDMA01 = r2->basicReq.daw, , tb = Z(0 - rf);
// Load rsDMA in case input buffer is a DMA buffer Test to see if there is any
data to transfer
if (tb) goto execSibling_2ind1 after {
r5 = rf + (-1);
r6 = r1->dma_entryPoint; // r6 = entry point of sibling task
r1 = r1->dma_SPBptr, // r1 = pointer to sibling task's SPB
, ind = r6; // Load entry point of sibling task
}
rsConfig23 = r0->dma_strmRsConfig;
// Load rsConfig for output buffer (never a DMA buffer)
r4 = r0->dma_outBufPtr;
rsa0 = r2->strmBufPtr;
// rsa0 = input buffer pointer
for (i = r5; i >= 0; --i)
after {
rsa2 = r4;
// rsa2 = output buffer pointer
nop;
nop;
}
//*****************************
// TODO: cycles to this point *
//*****************************
{
acc0 = (rsd0 = *rsa0++1);
// get sample
nop; // Those "nop"'s are really uggly, but there's
nop; // something with DSP's pipelines which I don't
nop; // understand, resulting this code to fail without
// having those "nop"'s (Benny)
rsa0?reqDMA = r2;
// Trigger DMA transfer on input stream,
// if needed to replenish input buffer
nop;
// Yet another magic "nop" to make stuff work
,,r98 = acc0 $+>> 0;
// store sample in ALU
nop;
// latency on load register.
// (this one is understandable)
*rsa2++1 = r98;
// store sample in output buffer
nop; // The same story
nop; // as above again ...
nop;
}
// TODO: cycles per loop iteration
r2->strmBufPtr = rsa0,, ;
// Update the modified buffer pointers
r4 = rsa2;
// Load output pointer position into r4
r2 = r0->nextSCB;
// Sibling task
goto execSibling_2ind1 // takes 6 cycles
after {
r98 = r2->thisSPB:entryPoint;
// Load child routine entry and data address
r1 = r9;
// r9 is r2->thisSPB
r0->dma_outBufPtr = r4,,
// Store updated output buffer pointer
ind = r8;
// r8 is r2->entryPoint
}
}
--- NEW FILE: cwcdma.h ---
/* generated from cwcdma.osp DO NOT MODIFY */
#ifndef __HEADER_cwcdma_H__
#define __HEADER_cwcdma_H__
symbol_entry_t cwcdma_symbols[] = {
{ 0x8000, "EXECCHILD",0x03 },
{ 0x8001, "EXECCHILD_98",0x03 },
{ 0x8003, "EXECCHILD_PUSH1IND",0x03 },
{ 0x8008, "EXECSIBLING",0x03 },
{ 0x800a, "EXECSIBLING_298",0x03 },
{ 0x800b, "EXECSIBLING_2IND1",0x03 },
{ 0x8010, "TIMINGMASTER",0x03 },
{ 0x804f, "S16_CODECINPUTTASK",0x03 },
{ 0x805e, "PCMSERIALINPUTTASK",0x03 },
{ 0x806d, "S16_MIX_TO_OSTREAM",0x03 },
{ 0x809a, "S16_MIX",0x03 },
{ 0x80bb, "S16_UPSRC",0x03 },
{ 0x813b, "MIX3_EXP",0x03 },
{ 0x8164, "DECIMATEBYPOW2",0x03 },
{ 0x8197, "VARIDECIMATE",0x03 },
{ 0x81f2, "_3DINPUTTASK",0x03 },
{ 0x820a, "_3DPRLGCINPTASK",0x03 },
{ 0x8227, "_3DSTEREOINPUTTASK",0x03 },
{ 0x8242, "_3DOUTPUTTASK",0x03 },
{ 0x82c4, "HRTF_MORPH_TASK",0x03 },
{ 0x82c6, "WAIT4DATA",0x03 },
{ 0x82fa, "PROLOGIC",0x03 },
{ 0x8496, "DECORRELATOR",0x03 },
{ 0x84a4, "STEREO2MONO",0x03 },
{ 0x0000, "OVERLAYBEGINADDRESS",0x00 },
{ 0x0000, "DMAREADER",0x03 },
{ 0x0018, "#CODE_END",0x00 },
}; /* cwcdma symbols */
u32 cwcdma_code[] = {
/* OVERLAYBEGINADDRESS */
/* 0000 */ 0x00002731,0x00001400,0x0004c108,0x000e5044,
/* 0002 */ 0x0005f608,0x00000000,0x000007ae,0x000be300,
/* 0004 */ 0x00058630,0x00001400,0x0007afb0,0x000e9584,
/* 0006 */ 0x00007301,0x000a9840,0x0005e708,0x000cd104,
/* 0008 */ 0x00067008,0x00000000,0x000902a0,0x00001000,
/* 000A */ 0x00012a01,0x000c0000,0x00000000,0x00000000,
/* 000C */ 0x00021843,0x000c0000,0x00000000,0x000c0000,
/* 000E */ 0x0000e101,0x000c0000,0x00000cac,0x00000000,
/* 0010 */ 0x00080000,0x000e5ca1,0x00000000,0x000c0000,
/* 0012 */ 0x00000000,0x00000000,0x00000000,0x00092c00,
/* 0014 */ 0x000122c1,0x000e5084,0x00058730,0x00001400,
/* 0016 */ 0x000d7488,0x000e4782,0x00007401,0x0001c100
};
/* #CODE_END */
segment_desc_t cwcdma_segments[] = {
{ SEGTYPE_SP_PROGRAM, 0x00000000, 0x00000030, cwcdma_code },
};
dsp_module_desc_t cwcdma_module = {
"cwcdma",
{
27,
cwcdma_symbols
},
1,
cwcdma_segments,
};
#endif /* __HEADER_cwcdma_H__ */
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