[PATCH 05/14] drm/amdgpu: add set_reg_remap callback for NBIO 7.9

[Alex Deucher]

This will be used to consolidate the register remap offset
configuration and fix  HDP flushes on systems non-4K pages.

Reviewed-by: Felix Kuehling <felix.kuehl...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
index 40d1e209eab7a..c2e78294c4fdc 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
@@ -475,6 +475,23 @@ static u64 nbio_v7_9_get_pcie_replay_count(struct 
amdgpu_device *adev)
        return (nak_r + nak_g);
 }
 
+#define MMIO_REG_HOLE_OFFSET 0x1A000
+
+static void nbio_v7_9_set_reg_remap(struct amdgpu_device *adev)
+{
+       if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
+               adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
+               adev->rmmio_remap.bus_addr = adev->rmmio_base + 
MMIO_REG_HOLE_OFFSET;
+       } else {
+               adev->rmmio_remap.reg_offset =
+                       SOC15_REG_OFFSET(
+                               NBIO, 0,
+                               
regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)
+                       << 2;
+               adev->rmmio_remap.bus_addr = 0;
+       }
+}
+
 const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
        .get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset,
        .get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset,
@@ -499,6 +516,7 @@ const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
        .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
        .init_registers = nbio_v7_9_init_registers,
        .get_pcie_replay_count = nbio_v7_9_get_pcie_replay_count,
+       .set_reg_remap = nbio_v7_9_set_reg_remap,
 };
 
 static void nbio_v7_9_query_ras_error_count(struct amdgpu_device *adev,
-- 
2.44.0