[PATCH 08/14] drm/amdgpu: add set_reg_remap callback for NBIO 2.3

[Alex Deucher]

This will be used to consolidate the register remap offset
configuration and fix  HDP flushes on systems non-4K pages.

Reviewed-by: Felix Kuehling <felix.kuehl...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index df218d5ca775c..41ae0a6f9db86 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -553,6 +553,20 @@ static void nbio_v2_3_clear_doorbell_interrupt(struct 
amdgpu_device *adev)
        }
 }
 
+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
+
+static void nbio_v2_3_set_reg_remap(struct amdgpu_device *adev)
+{
+       if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
+               adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
+               adev->rmmio_remap.bus_addr = adev->rmmio_base + 
MMIO_REG_HOLE_OFFSET;
+       } else {
+               adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+                       mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 
2;
+               adev->rmmio_remap.bus_addr = 0;
+       }
+}
+
 const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
        .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
        .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
@@ -577,4 +591,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
        .apply_lc_spc_mode_wa = nbio_v2_3_apply_lc_spc_mode_wa,
        .apply_l1_link_width_reconfig_wa = 
nbio_v2_3_apply_l1_link_width_reconfig_wa,
        .clear_doorbell_interrupt = nbio_v2_3_clear_doorbell_interrupt,
+       .set_reg_remap = nbio_v2_3_set_reg_remap,
 };
-- 
2.44.0