Am 28.05.24 um 19:23 schrieb Yunxiang Li:
If a reset is triggered, there's no point in waiting for the fence back
anymore, it just makes the reset code wait for a long time for the
reset_domain read lock to be dropped.
This also makes our reply to host FLR fast enough so the host doesn't
timeout.
Signed-off-by: Yunxiang Li <yunxiang...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 7 +++++--
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 2 +-
5 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 10832b470448..3c04f034d43e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -376,10 +376,12 @@ signed long amdgpu_fence_wait_polling(struct amdgpu_ring
*ring,
uint32_t wait_seq,
signed long timeout)
{
-
+ int in_reset = amdgpu_in_reset(ring->adev);
while ((int32_t)(wait_seq - amdgpu_fence_read(ring)) > 0 && timeout >
0) {
udelay(2);
timeout -= 2;
+ if (!in_reset && amdgpu_in_reset(ring->adev))
Clear NAK to that approach. This is just a pretty unstable hack.
It's perfectly possible that the reset has already started before we
enter the function.
Regards,
Christian.
+ return 0;
}
return timeout > 0 ? timeout : 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 8c6b0987919f..dd22fd93f572 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -32,14 +32,17 @@
#define AMDGPU_MES_MAX_NUM_OF_QUEUES_PER_PROCESS 1024
#define AMDGPU_ONE_DOORBELL_SIZE 8
-signed long amdgpu_mes_fence_wait_polling(u64 *fence,
+signed long amdgpu_mes_fence_wait_polling(struct amdgpu_device *adev,
+ u64 *fence,
u64 wait_seq,
signed long timeout)
{
-
+ int in_reset = amdgpu_in_reset(adev);
while ((s64)(wait_seq - *fence) > 0 && timeout > 0) {
udelay(2);
timeout -= 2;
+ if (!in_reset && amdgpu_in_reset(adev))
+ return 0;
}
return timeout > 0 ? timeout : 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index b99a2b3cffe3..064cb3995a3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -340,7 +340,8 @@ struct amdgpu_mes_funcs {
#define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
#define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev))
-signed long amdgpu_mes_fence_wait_polling(u64 *fence,
+signed long amdgpu_mes_fence_wait_polling(struct amdgpu_device *adev,
+ u64 *fence,
u64 wait_seq,
signed long timeout);
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 96629d8130b8..38edd60c6789 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -212,7 +212,7 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct
amdgpu_mes *mes,
else
dev_dbg(adev->dev, "MES msg=%d was emitted\n",
x_pkt->header.opcode);
- r = amdgpu_mes_fence_wait_polling(fence_ptr, (u64)1, timeout);
+ r = amdgpu_mes_fence_wait_polling(adev, fence_ptr, (u64)1, timeout);
amdgpu_device_wb_free(adev, fence_offset);
if (r < 1) {
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index c5a03b79f07e..73430b9c4b27 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -202,7 +202,7 @@ static int mes_v12_0_submit_pkt_and_poll_completion(struct
amdgpu_mes *mes,
else
dev_dbg(adev->dev, "MES msg=%d was emitted\n",
x_pkt->header.opcode);
- r = amdgpu_mes_fence_wait_polling(fence_ptr, (u64)1, timeout);
+ r = amdgpu_mes_fence_wait_polling(adev, fence_ptr, (u64)1, timeout);
amdgpu_device_wb_free(adev, fence_offset);
if (r < 1) {
