[AMD Official Use Only - AMD Internal Distribution Only] Series is
Reviewed-by: Hawking Zhang <[email protected]> Regards, Hawking -----Original Message----- From: Chai, Thomas <[email protected]> Sent: Saturday, October 11, 2025 15:48 To: [email protected] Cc: Zhang, Hawking <[email protected]>; Zhou1, Tao <[email protected]>; Li, Candice <[email protected]>; Wang, Yang(Kevin) <[email protected]>; Yang, Stanley <[email protected]>; Su, Joe <[email protected]>; Chai, Thomas <[email protected]>; Zhou1, Tao <[email protected]> Subject: [PATCH 9/9] drm/amdgpu: Add ras module eeprom safety watermark check Add ras module eeprom safety watermark check. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 3eb3fb55ccb0..5a7bf0661dbf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -32,6 +32,7 @@ #include <linux/uaccess.h> #include "amdgpu_reset.h" +#include "amdgpu_ras_mgr.h" /* These are memory addresses as would be seen by one or more EEPROM * chips strung on the I2C bus, usually by manipulating pins 1-3 of a @@ -556,6 +557,9 @@ bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + if (amdgpu_uniras_enabled(adev)) + return amdgpu_ras_mgr_check_eeprom_safety_watermark(adev); + if (!__is_ras_eeprom_supported(adev) || !amdgpu_bad_page_threshold) return false; -- 2.34.1
