On Mon, Oct 20, 2025 at 3:56 PM Rodrigo Siqueira <[email protected]> wrote: > > This commit expands the overall explanation about AMD GPU IPs by adding > more details about their interconnection. Note that this commit includes > a diagram that provides additional information. > > Cc: Alex Deucher <[email protected]> > Cc: Christian König <[email protected]> > Cc: Timur Kristóf <[email protected]> > Signed-off-by: Rodrigo Siqueira <[email protected]> > --- > .../gpu/amdgpu/amd_overview_block.svg | 674 ++++++++++++++++++ > Documentation/gpu/amdgpu/amdgpu-glossary.rst | 3 + > Documentation/gpu/amdgpu/driver-core.rst | 25 + > 3 files changed, 702 insertions(+) > create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg > > diff --git a/Documentation/gpu/amdgpu/amd_overview_block.svg > b/Documentation/gpu/amdgpu/amd_overview_block.svg > new file mode 100644 > index 000000000000..8d9ae95bd9a5 > --- /dev/null > +++ b/Documentation/gpu/amdgpu/amd_overview_block.svg
Got a link to the diagram anywhere? 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b/Documentation/gpu/amdgpu/amdgpu-glossary.rst > @@ -227,6 +227,9 @@ we have a dedicated glossary for Display Core at > TOC > Table of Contents > > + UMC > + Unified Memory Controller > + > UMSCH > User Mode Scheduler > > diff --git a/Documentation/gpu/amdgpu/driver-core.rst > b/Documentation/gpu/amdgpu/driver-core.rst > index 3ce276272171..13f13e2e5497 100644 > --- a/Documentation/gpu/amdgpu/driver-core.rst > +++ b/Documentation/gpu/amdgpu/driver-core.rst > @@ -77,6 +77,31 @@ VCN (Video Core Next) > decode. It's exposed to userspace for user mode drivers (VA-API, > OpenMAX, etc.) > > +It is important to note that these blocks can interact with each other. The > +picture below illustrates some of the components and their interconnection: > + > +.. kernel-figure:: amd_overview_block.svg > + > +In the diagram, memory-related blocks are represented by a green color. > Notice > +that specific IPs have a green block that represents a small hardware block > +named 'hub', which is responsible for interfacing with memory (pre-vega > devices > +have a dedicated block for that, named GMC). In the driver code, you can > +identify this component by looking for the suffix hub, for example: gfxhub, > +dchub, mmhub, vmhub, etc. All memory hubs are connected in the UMC, which in All memory hubs are connected to the UMCs, which in > +turn is connected to memory blocks. > + > +There is some level of protection for certain elements in memory, and the PSP > +plays an essential role in this area. For example, when a specific firmware > is > +loaded into the memory, PSP takes an action to ensure that the firmware has a > +valid signature. It also stores the firmware images in a protected memory area (TMR = Trusted Memory Area) so the OS or driver can't corrupt it at runtime after it's been validated. > Another use of PSP is to support the TA (e.g., HDCP) and TA = Trusted Application Basically small application that runs on the trusted processor and handles a trusted operation. > +encrypted memory via TMZ. TMZ (Trusted Memory Zone -- encrypted memory for content protection). > + > +Another IP that deserves attention is the SMU, as it is connected to all the > +other IPs. SMU will help put the GPU in optimal utilization by taking into > +account performance and power consumption. SMU helps other blocks to set up a > +proper clock configuration. Another feature of SMU is the support for > resetting > +every component. How about something like: Another important IP is the SMU. It handles reset distribution as well as clock and power management for all of the IPs on the SoC. Alex > + > .. _pipes-and-queues-description: > > GFX, Compute, and SDMA Overall Behavior > -- > 2.51.0 >
