On Mon, Oct 20, 2025 at 3:47 PM Rodrigo Siqueira <[email protected]> wrote: > > This commit introduces a diagram and a set of information that details > the different sets of schedulers available in the SE. > > Cc: Alex Deucher <[email protected]> > Cc: Christian König <[email protected]> > Cc: Timur Kristóf <[email protected]> > Signed-off-by: Rodrigo Siqueira <[email protected]>
Reviewed-by: Alex Deucher <[email protected]> > --- > Documentation/gpu/amdgpu/gc/index.rst | 24 +++++++++++++----------- > 1 file changed, 13 insertions(+), 11 deletions(-) > > diff --git a/Documentation/gpu/amdgpu/gc/index.rst > b/Documentation/gpu/amdgpu/gc/index.rst > index ff6e9ef5cbee..b6b583c9dc6a 100644 > --- a/Documentation/gpu/amdgpu/gc/index.rst > +++ b/Documentation/gpu/amdgpu/gc/index.rst > @@ -7,19 +7,21 @@ > The relationship between the CPU and GPU can be described as the > producer-consumer problem, where the CPU fills out a buffer with operations > (producer) to be executed by the GPU (consumer). The requested operations in > -the buffer are called Command Packets, which can be summarized as a > compressed > -way of transmitting command information to the graphics controller. > +the buffer are called **Command Packets**, which can be summarized as a > +compressed way of transmitting command information to the graphics > controller. > > The component that acts as the front end between the CPU and the GPU is > called > -the Command Processor (CP). This component is responsible for providing > greater > -flexibility to the GC since CP makes it possible to program various aspects > of > -the GPU pipeline. CP also coordinates the communication between the CPU and > GPU > -via a mechanism named **Ring Buffers**, where the CPU appends information to > -the buffer while the GPU removes operations. It is relevant to highlight > that a > -CPU can add a pointer to the Ring Buffer that points to another region of > -memory outside the Ring Buffer, and CP can handle it; this mechanism is > called > -**Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), > and > -writes the operations to the correct hardware blocks. > +**Command Processor (CP)**. This component is responsible for providing > greater > +flexibility to the **Graphics and Compute (GC)** since CP makes it possible > to > +program various aspects of the GPU pipeline. CP also coordinates the > +communication between the CPU and GPU via a mechanism named **Ring Buffers**, > +where the CPU appends information to the buffer while the GPU removes > +operations. CP is also responsible for handling **Indirect Buffers (IB)**. > + > +For reference, internally the CP consists of several sub-blocks (CPC - CP > +compute, CPG - CP graphics, and CPF - CP fetcher). Some of these acronyms > +appear in register names, but this is more of an implementation detail and > not > +something that directly impacts driver programming or debugging. > > Graphics (GFX) and Compute Microcontrollers > ------------------------------------------- > -- > 2.51.0 >
