Move se cac access callbacks to register access block.
Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++-----
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
.../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 24 +++++++++++++++++++
.../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 4 ++++
drivers/gpu/drm/amd/amdgpu/soc15.c | 12 +++++-----
5 files changed, 36 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 95defe443a5d..4f22b7da4657 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -906,10 +906,6 @@ struct amdgpu_device {
amdgpu_wreg64_t pcie_wreg64;
amdgpu_rreg64_ext_t pcie_rreg64_ext;
amdgpu_wreg64_ext_t pcie_wreg64_ext;
- /* protects concurrent se_cac register access */
- spinlock_t se_cac_idx_lock;
- amdgpu_rreg_t se_cac_rreg;
- amdgpu_wreg_t se_cac_wreg;
/* protects concurrent ENDPOINT (audio) register access */
spinlock_t audio_endpt_idx_lock;
amdgpu_block_rreg_t audio_endpt_rreg;
@@ -1318,8 +1314,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
#define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v))
#define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg))
#define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v))
-#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
-#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
+#define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg))
+#define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v))
#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block),
(reg))
#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev,
(block), (reg), (v))
#define WREG32_P(reg, val, mask) \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ef4c91482061..137ddce64536 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3908,7 +3908,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
spin_lock_init(&adev->mmio_idx_lock);
spin_lock_init(&adev->pcie_idx_lock);
- spin_lock_init(&adev->se_cac_idx_lock);
spin_lock_init(&adev->audio_endpt_idx_lock);
spin_lock_init(&adev->mm_stats.lock);
spin_lock_init(&adev->virt.rlcg_reg_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
index 69db9de507c5..d75ef23581a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
@@ -50,6 +50,10 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev)
spin_lock_init(&adev->reg.gc_cac.lock);
adev->reg.gc_cac.rreg = NULL;
adev->reg.gc_cac.wreg = NULL;
+
+ spin_lock_init(&adev->reg.se_cac.lock);
+ adev->reg.se_cac.rreg = NULL;
+ adev->reg.se_cac.wreg = NULL;
}
uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg)
@@ -129,6 +133,26 @@ void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev,
uint32_t reg,
adev->reg.gc_cac.wreg(adev, reg, v);
}
+uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg)
+{
+ if (!adev->reg.se_cac.rreg) {
+ dev_err_once(adev->dev, "SE_CAC register read not supported\n");
+ return 0;
+ }
+ return adev->reg.se_cac.rreg(adev, reg);
+}
+
+void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg,
+ uint32_t v)
+{
+ if (!adev->reg.se_cac.wreg) {
+ dev_err_once(adev->dev,
+ "SE_CAC register write not supported\n");
+ return;
+ }
+ adev->reg.se_cac.wreg(adev, reg, v);
+}
+
/*
* register access helper functions.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
index 3736fd571771..63929999cd76 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
@@ -43,6 +43,7 @@ struct amdgpu_reg_access {
struct amdgpu_reg_ind uvd_ctx;
struct amdgpu_reg_ind didt;
struct amdgpu_reg_ind gc_cac;
+ struct amdgpu_reg_ind se_cac;
};
void amdgpu_reg_access_init(struct amdgpu_device *adev);
@@ -55,6 +56,9 @@ void amdgpu_reg_didt_wr32(struct amdgpu_device *adev,
uint32_t reg, uint32_t v);
uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg);
void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg,
uint32_t v);
+uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg);
+void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg,
+ uint32_t v);
typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t);
typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 534cd336a9b6..64e47435d9e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -320,10 +320,10 @@ static u32 soc15_se_cac_rreg(struct amdgpu_device *adev,
u32 reg)
unsigned long flags;
u32 r;
- spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
+ spin_lock_irqsave(&adev->reg.se_cac.lock, flags);
WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
- spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
+ spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags);
return r;
}
@@ -331,10 +331,10 @@ static void soc15_se_cac_wreg(struct amdgpu_device *adev,
u32 reg, u32 v)
{
unsigned long flags;
- spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
+ spin_lock_irqsave(&adev->reg.se_cac.lock, flags);
WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
- spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
+ spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags);
}
static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
@@ -975,8 +975,8 @@ static int soc15_common_early_init(struct amdgpu_ip_block
*ip_block)
adev->reg.didt.wreg = &soc15_didt_wreg;
adev->reg.gc_cac.rreg = &soc15_gc_cac_rreg;
adev->reg.gc_cac.wreg = &soc15_gc_cac_wreg;
- adev->se_cac_rreg = &soc15_se_cac_rreg;
- adev->se_cac_wreg = &soc15_se_cac_wreg;
+ adev->reg.se_cac.rreg = &soc15_se_cac_rreg;
+ adev->reg.se_cac.wreg = &soc15_se_cac_wreg;
adev->rev_id = amdgpu_device_get_rev_id(adev);
adev->external_rev_id = 0xFF;
--
2.49.0
