add initialization func for pmfw eeprom
Signed-off-by: Gangliang Xie <[email protected]>
---
drivers/gpu/drm/amd/ras/rascore/ras_core.c | 15 +++-
.../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c | 84 +++++++++++++++++++
.../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h | 2 +
3 files changed, 98 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
index fe188a5304d9..1eba279a020b 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
@@ -387,7 +387,10 @@ int ras_core_hw_init(struct ras_core_context *ras_core)
ras_fw_init_feature_flags(ras_core);
- ret = ras_eeprom_hw_init(ras_core);
+ if (ras_fw_eeprom_supported(ras_core))
+ ret = ras_fw_eeprom_hw_init(ras_core);
+ else
+ ret = ras_eeprom_hw_init(ras_core);
if (ret)
goto init_err6;
@@ -411,7 +414,10 @@ int ras_core_hw_init(struct ras_core_context *ras_core)
return 0;
init_err7:
- ras_eeprom_hw_fini(ras_core);
+ if (ras_fw_eeprom_supported(ras_core))
+ ras_fw_eeprom_hw_fini(ras_core);
+ else
+ ras_eeprom_hw_fini(ras_core);
init_err6:
ras_gfx_hw_fini(ras_core);
init_err5:
@@ -432,7 +438,10 @@ int ras_core_hw_fini(struct ras_core_context *ras_core)
ras_core->is_initialized = false;
ras_process_fini(ras_core);
- ras_eeprom_hw_fini(ras_core);
+ if (ras_fw_eeprom_supported(ras_core))
+ ras_fw_eeprom_hw_fini(ras_core);
+ else
+ ras_eeprom_hw_fini(ras_core);
ras_gfx_hw_fini(ras_core);
ras_nbio_hw_fini(ras_core);
ras_umc_hw_fini(ras_core);
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
index 7a2c14f276b5..138d223a1256 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
@@ -369,3 +369,87 @@ int ras_fw_eeprom_update_record(struct ras_core_context
*ras_core,
return ret;
}
+
+static int __check_ras_fw_table_status(struct ras_core_context *ras_core)
+{
+ struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
+ uint64_t local_time;
+ int res;
+
+ mutex_init(&control->ras_tbl_mutex);
+
+ res = ras_fw_get_table_version(ras_core, &(control->version));
+ if (res)
+ return res;
+
+ res = ras_fw_get_badpage_count(ras_core, &(control->ras_num_recs), 100);
+ if (res)
+ return res;
+
+ local_time = (uint64_t)ktime_get_real_seconds();
+ res = ras_fw_set_timestamp(ras_core, local_time);
+ if (res)
+ return res;
+
+ control->ras_max_record_count = 4000;
+
+
+ if (control->ras_num_recs > control->ras_max_record_count) {
+ RAS_DEV_ERR(ras_core->dev,
+ "RAS header invalid, records in header: %u max allowed
:%u",
+ control->ras_num_recs, control->ras_max_record_count);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core)
+{
+ struct ras_fw_eeprom_control *control;
+ struct ras_eeprom_config *eeprom_cfg;
+ struct ras_mp1 *mp1;
+ const struct ras_mp1_sys_func *sys_func;
+
+ if (!ras_core)
+ return -EINVAL;
+
+ mp1 = &ras_core->ras_mp1;
+ sys_func = mp1->sys_func;
+
+ if (!sys_func || !sys_func->mp1_send_eeprom_msg)
+ return -EINVAL;
+
+ ras_core->is_rma = false;
+
+ control = &ras_core->ras_fw_eeprom;
+
+ memset(control, 0, sizeof(*control));
+
+ eeprom_cfg = &ras_core->config->eeprom_cfg;
+ control->record_threshold_config =
+ eeprom_cfg->eeprom_record_threshold_config;
+
+ control->record_threshold_count = 4000;
+ if (eeprom_cfg->eeprom_record_threshold_count <
+ control->record_threshold_count)
+ control->record_threshold_count =
+ eeprom_cfg->eeprom_record_threshold_count;
+
+ control->update_channel_flag = false;
+
+ return __check_ras_fw_table_status(ras_core);
+}
+
+int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core)
+{
+ struct ras_fw_eeprom_control *control;
+
+ if (!ras_core)
+ return -EINVAL;
+
+ control = &ras_core->ras_fw_eeprom;
+ mutex_destroy(&control->ras_tbl_mutex);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
index ed8ebdf22156..5966955cd847 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
@@ -77,5 +77,7 @@ int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core,
uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core);
int ras_fw_eeprom_update_record(struct ras_core_context *ras_core,
struct ras_bank_ecc *ras_ecc);
+int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core);
+int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core);
#endif
--
2.34.1
