Slightly refactor and simplify DAC load detection. This prepares the code to be used for also executing DAC load detection on external DP bridge encoders.
DAC load detection belongs better in the hardware sequencer code because the implementation is HW dependent and not all chips support the functionality. The code is cleaner when link detection probably doesn't call the VBIOS directly. Signed-off-by: Timur Kristóf <[email protected]> --- .../gpu/drm/amd/display/dc/bios/bios_parser.c | 25 ++++++++----------- .../gpu/drm/amd/display/dc/dc_bios_types.h | 4 +-- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 12 +++++++++ .../drm/amd/display/dc/hwss/hw_sequencer.h | 1 + .../drm/amd/display/dc/link/link_detection.c | 24 +++--------------- 5 files changed, 28 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 9f11e6ca4051..e2b74dda00fc 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -782,26 +782,17 @@ static enum bp_result bios_parser_encoder_control( static enum bp_result bios_parser_dac_load_detection( struct dc_bios *dcb, - enum engine_id engine_id, - enum dal_device_type device_type, - uint32_t enum_id) + enum engine_id engine_id) { struct bios_parser *bp = BP_FROM_DCB(dcb); struct dc_context *ctx = dcb->ctx; struct bp_load_detection_parameters bp_params = {0}; - enum bp_result bp_result; + enum bp_result bp_result = BP_RESULT_UNSUPPORTED; uint32_t bios_0_scratch; uint32_t device_id_mask = 0; - bp_params.engine_id = engine_id; - bp_params.device_id = get_support_mask_for_device_id(device_type, enum_id); - - if (engine_id != ENGINE_ID_DACA && - engine_id != ENGINE_ID_DACB) - return BP_RESULT_UNSUPPORTED; - - if (!bp->cmd_tbl.dac_load_detection) - return BP_RESULT_UNSUPPORTED; + bp_params.device_id = get_support_mask_for_device_id( + DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1); if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT) device_id_mask = ATOM_S0_CRT1_MASK; @@ -815,7 +806,13 @@ static enum bp_result bios_parser_dac_load_detection( bios_0_scratch &= ~device_id_mask; dm_write_reg(ctx, bp->base.regs->BIOS_SCRATCH_0, bios_0_scratch); - bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params); + if (engine_id == ENGINE_ID_DACA || engine_id == ENGINE_ID_DACB) { + if (!bp->cmd_tbl.dac_load_detection) + return BP_RESULT_UNSUPPORTED; + + bp_params.engine_id = engine_id; + bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params); + } if (bp_result != BP_RESULT_OK) return bp_result; diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 40d7a7d83c40..06fdde281a0c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -99,9 +99,7 @@ struct dc_vbios_funcs { struct bp_encoder_control *cntl); enum bp_result (*dac_load_detection)( struct dc_bios *bios, - enum engine_id engine_id, - enum dal_device_type device_type, - uint32_t enum_id); + enum engine_id engine_id); enum bp_result (*transmitter_control)( struct dc_bios *bios, struct bp_transmitter_control *cntl); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 4659e1b489ba..4e820020252b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -674,6 +674,17 @@ dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable) bios->funcs->encoder_control(bios, &encoder_control); } +static bool +dce110_dac_load_detect(struct dc_link *link) +{ + struct dc_bios *bios = link->ctx->dc_bios; + struct link_encoder *link_enc = link->link_enc; + enum bp_result bp_result = BP_RESULT_FAILURE; + + bp_result = bios->funcs->dac_load_detection(bios, link_enc->analog_engine); + return bp_result == BP_RESULT_OK; +} + void dce110_enable_stream(struct pipe_ctx *pipe_ctx) { enum dc_lane_count lane_count = @@ -3442,6 +3453,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .enable_tmds_link_output = dce110_enable_tmds_link_output, .enable_dp_link_output = dce110_enable_dp_link_output, .disable_link_output = dce110_disable_link_output, + .dac_load_detect = dce110_dac_load_detect, }; static const struct hwseq_private_funcs dce110_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 51b0f0fd8fcd..5c9a758fde37 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -1187,6 +1187,7 @@ struct hw_sequencer_funcs { void (*disable_link_output)(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal); + bool (*dac_load_detect)(struct dc_link *link); void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 578509e8d0e2..1585cce65b0e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -932,28 +932,10 @@ static bool link_detect_ddc_probe(struct dc_link *link) */ static bool link_detect_dac_load_detect(struct dc_link *link) { - struct dc_bios *bios = link->ctx->dc_bios; - struct link_encoder *link_enc = link->link_enc; - enum engine_id engine_id = link_enc->preferred_engine; - enum dal_device_type device_type = DEVICE_TYPE_CRT; - enum bp_result bp_result = BP_RESULT_UNSUPPORTED; - uint32_t enum_id; - - switch (engine_id) { - case ENGINE_ID_DACB: - enum_id = 2; - break; - case ENGINE_ID_DACA: - default: - engine_id = ENGINE_ID_DACA; - enum_id = 1; - break; - } - - if (bios->funcs->dac_load_detection) - bp_result = bios->funcs->dac_load_detection(bios, engine_id, device_type, enum_id); + if (!link->dc->hwss.dac_load_detect) + return false; - return bp_result == BP_RESULT_OK; + return link->dc->hwss.dac_load_detect(link); } /* -- 2.52.0
