Remove the legacy get_retire_flip_bits implementation for UMC v12
Signed-off-by: Ce Sun <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 106 -------------------------
1 file changed, 106 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
index d62712324940..d3eeaead7ca2 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
@@ -73,115 +73,9 @@ bool umc_v12_0_is_correctable_error(struct amdgpu_device
*adev, uint64_t mc_umc_
!(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)))));
}
-static void umc_v12_0_get_retire_flip_bits(struct amdgpu_device *adev)
-{
- enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE;
- uint32_t vram_type = adev->gmc.vram_type;
- struct amdgpu_umc_flip_bits *flip_bits = &(adev->umc.flip_bits);
-
- if (adev->gmc.gmc_funcs->query_mem_partition_mode)
- nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
-
- if (adev->gmc.num_umc == 16) {
- /* default setting */
- flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT;
- flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT;
- flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT;
- flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT;
- flip_bits->flip_row_bit = 13;
- flip_bits->bit_num = 4;
- flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT;
-
- if (nps == AMDGPU_NPS2_PARTITION_MODE) {
- flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;
- flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;
- flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;
- flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT;
- } else if (nps == AMDGPU_NPS4_PARTITION_MODE) {
- flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;
- flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;
- flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;
- flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;
- }
-
- switch (vram_type) {
- case AMDGPU_VRAM_TYPE_HBM:
- /* other nps modes are taken as nps1 */
- if (nps == AMDGPU_NPS2_PARTITION_MODE)
- flip_bits->flip_bits_in_pa[3] =
UMC_V12_0_PA_R12_BIT;
- else if (nps == AMDGPU_NPS4_PARTITION_MODE)
- flip_bits->flip_bits_in_pa[3] =
UMC_V12_0_PA_R11_BIT;
-
- break;
- case AMDGPU_VRAM_TYPE_HBM3E:
- flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
- flip_bits->flip_row_bit = 12;
-
- if (nps == AMDGPU_NPS2_PARTITION_MODE)
- flip_bits->flip_bits_in_pa[3] =
UMC_V12_0_PA_R11_BIT;
- else if (nps == AMDGPU_NPS4_PARTITION_MODE)
- flip_bits->flip_bits_in_pa[3] =
UMC_V12_0_PA_R10_BIT;
-
- break;
- default:
- dev_warn(adev->dev,
- "Unknown HBM type, set RAS retire flip bits to
the value in NPS1 mode.\n");
- break;
- }
- } else if (adev->gmc.num_umc == 8) {
- /* default setting */
- flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;
- flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;
- flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;
- flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
- flip_bits->flip_row_bit = 12;
- flip_bits->bit_num = 4;
- flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT;
-
- if (nps == AMDGPU_NPS2_PARTITION_MODE) {
- flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;
- flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;
- flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;
- flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;
- }
-
- switch (vram_type) {
- case AMDGPU_VRAM_TYPE_HBM:
- flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
-
- /* other nps modes are taken as nps1 */
- if (nps == AMDGPU_NPS2_PARTITION_MODE)
- flip_bits->flip_bits_in_pa[3] =
UMC_V12_0_PA_R11_BIT;
-
- break;
- case AMDGPU_VRAM_TYPE_HBM3E:
- flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
- flip_bits->flip_row_bit = 12;
-
- if (nps == AMDGPU_NPS2_PARTITION_MODE)
- flip_bits->flip_bits_in_pa[3] =
UMC_V12_0_PA_R10_BIT;
-
- break;
- default:
- dev_warn(adev->dev,
- "Unknown HBM type, set RAS retire flip bits to
the value in NPS1 mode.\n");
- break;
- }
- } else {
- dev_warn(adev->dev,
- "Unsupported UMC number(%d), failed to set RAS flip
bits.\n",
- adev->gmc.num_umc);
-
- return;
- }
-
- adev->umc.retire_unit = 0x1 << flip_bits->bit_num;
-}
-
struct amdgpu_umc_ras umc_v12_0_ras = {
.ras_block = {
.hw_ops = NULL,
},
- .get_retire_flip_bits = umc_v12_0_get_retire_flip_bits,
};
--
2.34.1
