retire legacy umc v12_0 ras functions
Signed-off-by: Ce Sun <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +-
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 56 --------------
drivers/gpu/drm/amd/amdgpu/umc_v12_0.h | 74 -------------------
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 1 -
5 files changed, 6 insertions(+), 135 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
delete mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 5100e35027ec..3b9c3b7be482 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -113,7 +113,7 @@ amdgpu-y += \
# add UMC block
amdgpu-y += \
- umc_v6_0.o umc_v6_1.o umc_v6_7.o umc_v8_7.o umc_v8_10.o umc_v12_0.o
umc_v8_14.o
+ umc_v6_0.o umc_v6_1.o umc_v6_7.o umc_v8_7.o umc_v8_10.o umc_v8_14.o
# add IH block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 1fcc0594fd0a..f6eed1470647 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -56,7 +56,6 @@
#include "umc_v6_1.h"
#include "umc_v6_0.h"
#include "umc_v6_7.h"
-#include "umc_v12_0.h"
#include "ras_umc_v12_0.h"
#include "hdp_v4_0.h"
#include "mca_v3_0.h"
@@ -79,6 +78,8 @@
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2
0x05ea
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX
2
+struct amdgpu_umc_ras umc_dummy_ras;
+
static const char * const gfxhub_client_ids[] = {
"CB",
"DB",
@@ -1389,7 +1390,7 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device
*adev)
adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM;
adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET;
if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
- adev->umc.ras = &umc_v12_0_ras;
+ adev->umc.ras = &umc_dummy_ras;
break;
default:
break;
@@ -2271,7 +2272,8 @@ static int gmc_v9_0_hw_fini(struct amdgpu_ip_block
*ip_block)
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
if (adev->gmc.ecc_irq.funcs &&
- amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
+ amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
+ adev->umc.ras)
amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
deleted file mode 100644
index 99d19de42525..000000000000
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#include "umc_v12_0.h"
-#include "amdgpu_ras.h"
-#include "amdgpu_umc.h"
-#include "amdgpu.h"
-#include "umc/umc_12_0_0_offset.h"
-#include "umc/umc_12_0_0_sh_mask.h"
-#include "mp/mp_13_0_6_sh_mask.h"
-
-bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t
mc_umc_status)
-{
- return ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val)
== 1) &&
- (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC)
== 1 ||
- REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC)
== 1 ||
- REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC)
== 1));
-}
-
-bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t
mc_umc_status)
-{
- return (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val)
== 1 &&
- (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0,
CECC) == 1 ||
- (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0,
UECC) == 1 &&
- REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC)
== 0) ||
- /* Identify data parity error in replay mode */
- ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0,
ErrorCodeExt) == 0x5 ||
- REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0,
ErrorCodeExt) == 0xb) &&
- !(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)))));
-}
-
-struct amdgpu_umc_ras umc_v12_0_ras = {
- .ras_block = {
- .hw_ops = NULL,
- },
-};
-
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
deleted file mode 100644
index 906dc7fa1008..000000000000
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef __UMC_V12_0_H__
-#define __UMC_V12_0_H__
-
-#include "soc15_common.h"
-#include "amdgpu.h"
-
-/* one piece of normalized address is mapped to 8 pieces of physical address */
-#define UMC_V12_0_NA_MAP_PA_NUM 8
-/* R13 bit shift should be considered, double the number */
-#define UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL (UMC_V12_0_NA_MAP_PA_NUM * 2)
-
-/* column bits in SOC physical address */
-#define UMC_V12_0_PA_C2_BIT 15
-#define UMC_V12_0_PA_C3_BIT 16
-#define UMC_V12_0_PA_C4_BIT 21
-/* row bits in SOC physical address */
-#define UMC_V12_0_PA_R0_BIT 22
-#define UMC_V12_0_PA_R10_BIT 32
-#define UMC_V12_0_PA_R11_BIT 33
-#define UMC_V12_0_PA_R12_BIT 34
-#define UMC_V12_0_PA_R13_BIT 35
-/* channel bit in SOC physical address */
-#define UMC_V12_0_PA_CH4_BIT 12
-#define UMC_V12_0_PA_CH5_BIT 13
-/* bank bit in SOC physical address */
-#define UMC_V12_0_PA_B0_BIT 19
-#define UMC_V12_0_PA_B1_BIT 20
-/* row bits in MCA address */
-#define UMC_V12_0_MA_R0_BIT 10
-
-#define MCA_IPID_LO_2_UMC_CH(_ipid_lo) (((((_ipid_lo) >> 20) & 0x1) * 4) + \
- (((_ipid_lo) >> 12) & 0xF))
-#define MCA_IPID_LO_2_UMC_INST(_ipid_lo) (((_ipid_lo) >> 21) & 0x7)
-
-#define MCA_IPID_2_DIE_ID(ipid) ((REG_GET_FIELD(ipid, MCMP1_IPIDT0,
InstanceIdHi) >> 2) & 0x03)
-
-#define MCA_IPID_2_UMC_CH(ipid) \
- (MCA_IPID_LO_2_UMC_CH(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo)))
-
-#define MCA_IPID_2_UMC_INST(ipid) \
- (MCA_IPID_LO_2_UMC_INST(REG_GET_FIELD(ipid, MCMP1_IPIDT0,
InstanceIdLo)))
-
-#define MCA_IPID_2_SOCKET_ID(ipid) \
- (((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo) & 0x1) << 2) | \
- (REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) & 0x03))
-
-bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t
mc_umc_status);
-bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t
mc_umc_status);
-
-extern struct amdgpu_umc_ras umc_v12_0_ras;
-
-#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 7c5e04a1cc94..8a1e28e45a2e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -47,7 +47,6 @@
#include "smu_cmn.h"
#include "mp/mp_13_0_6_offset.h"
#include "mp/mp_13_0_6_sh_mask.h"
-#include "umc_v12_0.h"
#undef MP1_Public
#undef smnMP1_FIRMWARE_FLAGS
--
2.34.1
