retire legacy RAS reset/query operations for umc v12.0
Signed-off-by: Ce Sun <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 214 +------------------------
drivers/gpu/drm/amd/amdgpu/umc_v12_0.h | 25 ---
3 files changed, 3 insertions(+), 239 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 5166055c6692..1fcc0594fd0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -57,6 +57,7 @@
#include "umc_v6_0.h"
#include "umc_v6_7.h"
#include "umc_v12_0.h"
+#include "ras_umc_v12_0.h"
#include "hdp_v4_0.h"
#include "mca_v3_0.h"
@@ -1382,7 +1383,7 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device
*adev)
case IP_VERSION(12, 0, 0):
case IP_VERSION(12, 5, 0):
adev->umc.max_ras_err_cnt_per_query =
- UMC_V12_0_TOTAL_CHANNEL_NUM(adev) *
UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
+ UMC_V12_0_TOTAL_CHANNEL_NUM *
UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM;
adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM;
adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM;
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
index 328dd2e8d328..b74275800795 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
@@ -31,45 +31,6 @@
#define MAX_ECC_NUM_PER_RETIREMENT 32
#define DELAYED_TIME_FOR_GPU_RESET 1000 //ms
-static inline uint64_t get_umc_v12_0_reg_offset(struct amdgpu_device *adev,
- uint32_t node_inst,
- uint32_t umc_inst,
- uint32_t ch_inst)
-{
- uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst;
- uint64_t cross_node_offset = (node_inst == 0) ? 0 :
UMC_V12_0_CROSS_NODE_OFFSET;
-
- umc_inst = index / 4;
- ch_inst = index % 4;
-
- return adev->umc.channel_offs * ch_inst + UMC_V12_0_INST_DIST *
umc_inst +
- UMC_V12_0_NODE_DIST * node_inst + cross_node_offset;
-}
-
-static int umc_v12_0_reset_error_count_per_channel(struct amdgpu_device *adev,
- uint32_t node_inst, uint32_t umc_inst,
- uint32_t ch_inst, void *data)
-{
- uint64_t odecc_err_cnt_addr;
- uint64_t umc_reg_offset =
- get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst);
-
- odecc_err_cnt_addr =
- SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt);
-
- /* clear error count */
- WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4,
- UMC_V12_0_CE_CNT_INIT);
-
- return 0;
-}
-
-static void umc_v12_0_reset_error_count(struct amdgpu_device *adev)
-{
- amdgpu_umc_loop_channels(adev,
- umc_v12_0_reset_error_count_per_channel, NULL);
-}
-
bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t
mc_umc_status)
{
dev_dbg(adev->dev,
@@ -115,65 +76,6 @@ bool umc_v12_0_is_correctable_error(struct amdgpu_device
*adev, uint64_t mc_umc_
!(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)))));
}
-static void umc_v12_0_query_error_count_per_type(struct amdgpu_device *adev,
- uint64_t umc_reg_offset,
- unsigned long *error_count,
- check_error_type_func
error_type_func)
-{
- uint64_t mc_umc_status;
- uint64_t mc_umc_status_addr;
-
- mc_umc_status_addr =
- SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
-
- /* Check MCUMC_STATUS */
- mc_umc_status =
- RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4);
-
- if (error_type_func(adev, mc_umc_status))
- *error_count += 1;
-}
-
-static int umc_v12_0_query_error_count(struct amdgpu_device *adev,
- uint32_t node_inst, uint32_t umc_inst,
- uint32_t ch_inst, void *data)
-{
- struct ras_err_data *err_data = (struct ras_err_data *)data;
- unsigned long ue_count = 0, ce_count = 0, de_count = 0;
-
- /* NOTE: node_inst is converted by adev->umc.active_mask and the range
is [0-3],
- * which can be used as die ID directly */
- struct amdgpu_smuio_mcm_config_info mcm_info = {
- .socket_id = adev->smuio.funcs->get_socket_id(adev),
- .die_id = node_inst,
- };
-
- uint64_t umc_reg_offset =
- get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst);
-
- umc_v12_0_query_error_count_per_type(adev, umc_reg_offset,
- &ce_count,
umc_v12_0_is_correctable_error);
- umc_v12_0_query_error_count_per_type(adev, umc_reg_offset,
- &ue_count,
umc_v12_0_is_uncorrectable_error);
- umc_v12_0_query_error_count_per_type(adev, umc_reg_offset,
- &de_count,
umc_v12_0_is_deferred_error);
-
- amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count);
- amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count);
- amdgpu_ras_error_statistic_de_count(err_data, &mcm_info, de_count);
-
- return 0;
-}
-
-static void umc_v12_0_query_ras_error_count(struct amdgpu_device *adev,
- void *ras_error_status)
-{
- amdgpu_umc_loop_channels(adev,
- umc_v12_0_query_error_count, ras_error_status);
-
- umc_v12_0_reset_error_count(adev);
-}
-
static void umc_v12_0_get_retire_flip_bits(struct amdgpu_device *adev)
{
enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE;
@@ -371,98 +273,6 @@ static int umc_v12_0_convert_error_address(struct
amdgpu_device *adev,
return ret;
}
-static int umc_v12_0_query_error_address(struct amdgpu_device *adev,
- uint32_t node_inst, uint32_t umc_inst,
- uint32_t ch_inst, void *data)
-{
- struct ras_err_data *err_data = (struct ras_err_data *)data;
- struct ta_ras_query_address_input addr_in;
- uint64_t mc_umc_status_addr;
- uint64_t mc_umc_status, err_addr;
- uint64_t mc_umc_addrt0;
- uint64_t umc_reg_offset =
- get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst);
-
- mc_umc_status_addr =
- SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
-
- mc_umc_status = RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) *
4);
-
- if (mc_umc_status == 0)
- return 0;
-
- if (!err_data->err_addr) {
- /* clear umc status */
- WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4,
0x0ULL);
-
- return 0;
- }
-
- /* calculate error address if ue error is detected */
- if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status) ||
- umc_v12_0_is_deferred_error(adev, mc_umc_status)) {
- mc_umc_addrt0 =
- SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
-
- err_addr = RREG64_PCIE_EXT((mc_umc_addrt0 + umc_reg_offset) *
4);
-
- err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0,
ErrorAddr);
-
- if (!adev->aid_mask &&
- adev->smuio.funcs &&
- adev->smuio.funcs->get_socket_id)
- addr_in.ma.socket_id =
adev->smuio.funcs->get_socket_id(adev);
- else
- addr_in.ma.socket_id = 0;
-
- addr_in.ma.err_addr = err_addr;
- addr_in.ma.ch_inst = ch_inst;
- addr_in.ma.umc_inst = umc_inst;
- addr_in.ma.node_inst = node_inst;
-
- umc_v12_0_convert_error_address(adev, err_data, &addr_in, NULL,
true);
- }
-
- /* clear umc status */
- WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
-
- return 0;
-}
-
-static void umc_v12_0_query_ras_error_address(struct amdgpu_device *adev,
- void *ras_error_status)
-{
- amdgpu_umc_loop_channels(adev,
- umc_v12_0_query_error_address, ras_error_status);
-}
-
-static int umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device *adev,
- uint32_t node_inst, uint32_t umc_inst,
- uint32_t ch_inst, void *data)
-{
- uint32_t odecc_cnt_sel;
- uint64_t odecc_cnt_sel_addr, odecc_err_cnt_addr;
- uint64_t umc_reg_offset =
- get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst);
-
- odecc_cnt_sel_addr =
- SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccCntSel);
- odecc_err_cnt_addr =
- SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt);
-
- odecc_cnt_sel = RREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) *
4);
-
- /* set ce error interrupt type to APIC based interrupt */
- odecc_cnt_sel = REG_SET_FIELD(odecc_cnt_sel, UMCCH0_OdEccCntSel,
- OdEccErrInt, 0x1);
- WREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4,
odecc_cnt_sel);
-
- /* set error count to initial value */
- WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4,
UMC_V12_0_CE_CNT_INIT);
-
- return 0;
-}
-
static bool umc_v12_0_check_ecc_err_status(struct amdgpu_device *adev,
enum amdgpu_mca_error_type type, void *ras_error_status)
{
@@ -482,26 +292,6 @@ static bool umc_v12_0_check_ecc_err_status(struct
amdgpu_device *adev,
return false;
}
-static void umc_v12_0_err_cnt_init(struct amdgpu_device *adev)
-{
- amdgpu_umc_loop_channels(adev,
- umc_v12_0_err_cnt_init_per_channel, NULL);
-}
-
-static bool umc_v12_0_query_ras_poison_mode(struct amdgpu_device *adev)
-{
- /*
- * Force return true, because regUMCCH0_EccCtrl
- * is not accessible from host side
- */
- return true;
-}
-
-const struct amdgpu_ras_block_hw_ops umc_v12_0_ras_hw_ops = {
- .query_ras_error_count = umc_v12_0_query_ras_error_count,
- .query_ras_error_address = umc_v12_0_query_ras_error_address,
-};
-
static int umc_v12_0_update_ecc_status(struct amdgpu_device *adev,
uint64_t status, uint64_t ipid, uint64_t addr)
{
@@ -690,10 +480,8 @@ static void umc_v12_0_mca_ipid_parse(struct amdgpu_device
*adev, uint64_t ipid,
struct amdgpu_umc_ras umc_v12_0_ras = {
.ras_block = {
- .hw_ops = &umc_v12_0_ras_hw_ops,
+ .hw_ops = NULL,
},
- .err_cnt_init = umc_v12_0_err_cnt_init,
- .query_ras_poison_mode = umc_v12_0_query_ras_poison_mode,
.ecc_info_query_ras_error_address = umc_v12_0_query_ras_ecc_err_addr,
.check_ecc_err_status = umc_v12_0_check_ecc_err_status,
.update_ecc_status = umc_v12_0_update_ecc_status,
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
index 63b7e7254526..d470775be308 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
@@ -26,31 +26,6 @@
#include "soc15_common.h"
#include "amdgpu.h"
-#define UMC_V12_0_NODE_DIST 0x40000000
-#define UMC_V12_0_INST_DIST 0x40000
-
-/* UMC register per channel offset */
-#define UMC_V12_0_PER_CHANNEL_OFFSET 0x400
-
-/* UMC cross node offset */
-#define UMC_V12_0_CROSS_NODE_OFFSET 0x100000000
-
-/* OdEccErrCnt max value */
-#define UMC_V12_0_CE_CNT_MAX 0xffff
-/* umc ce interrupt threshold */
-#define UMC_V12_0_CE_INT_THRESHOLD 0xffff
-/* umc ce count initial value */
-#define UMC_V12_0_CE_CNT_INIT (UMC_V12_0_CE_CNT_MAX -
UMC_V12_0_CE_INT_THRESHOLD)
-
-/* number of umc channel instance with memory map register access */
-#define UMC_V12_0_CHANNEL_INSTANCE_NUM 8
-/* number of umc instance with memory map register access */
-#define UMC_V12_0_UMC_INSTANCE_NUM 4
-
-/* Total channel instances for all available umc nodes */
-#define UMC_V12_0_TOTAL_CHANNEL_NUM(adev) \
- (UMC_V12_0_CHANNEL_INSTANCE_NUM * (adev)->gmc.num_umc)
-
/* one piece of normalized address is mapped to 8 pieces of physical address */
#define UMC_V12_0_NA_MAP_PA_NUM 8
/* R13 bit shift should be considered, double the number */
--
2.34.1
