From: YiLing Chen <[email protected]> [Why & How] Apply the inbox0 lock mechanism for DCN35 to prevent racing with driver/FW.
This requires DMUB firmware 0.1.68.0 or newer. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: YiLing Chen <[email protected]> Signed-off-by: Tom Chung <[email protected]> --- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 43 +++++++++++++++++++ .../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 4 ++ .../amd/display/dc/hwss/dcn35/dcn35_init.c | 2 + .../amd/display/dc/hwss/dcn351/dcn351_init.c | 2 + 4 files changed, 51 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 6e1079377f48..09b59466ae7a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -1835,3 +1835,46 @@ void dcn35_disable_link_output(struct dc_link *link, dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); } + +void dcn35_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock) +{ + /* use always for now */ + union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; + + if (!dc->ctx || !dc->ctx->dmub_srv) + return; + + /* if not support inbox0 lock, would not use inbox0 lock mechanism */ + if (!dc->ctx->dmub_srv->dmub->meta_info.feature_bits.bits.inbox0_lock_support) + return; + + if (!dc_dmub_srv_is_cursor_offload_enabled(dc) && + !dmub_hw_lock_mgr_does_context_require_lock(dc, context)) + return; + + hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; + hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; + hw_lock_cmd.bits.lock = lock; + hw_lock_cmd.bits.should_release = !lock; + dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); +} + +void dcn35_dmub_hw_control_lock_fast(union block_sequence_params *params) +{ + struct dc *dc = params->dmub_hw_control_lock_fast_params.dc; + bool lock = params->dmub_hw_control_lock_fast_params.lock; + + /* if not support inbox0 lock, would not use inbox0 lock mechanism */ + if (!dc->ctx->dmub_srv->dmub->meta_info.feature_bits.bits.inbox0_lock_support) + return; + + if (params->dmub_hw_control_lock_fast_params.is_required) { + union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; + + hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; + hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; + hw_lock_cmd.bits.lock = lock; + hw_lock_cmd.bits.should_release = !lock; + dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); + } +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h index 235ebf00bd1f..e402e30f755d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h @@ -27,6 +27,8 @@ #ifndef __DC_HWSS_DCN35_H__ #define __DC_HWSS_DCN35_H__ +#include "inc/core_types.h" +#include "dc.h" #include "hw_sequencer_private.h" struct dc; @@ -113,5 +115,7 @@ void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe void dcn35_disable_link_output(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal); +void dcn35_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock); +void dcn35_dmub_hw_control_lock_fast(union block_sequence_params *params); #endif /* __DC_HWSS_DCN35_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c index fc18d2207711..56e5dfef126a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c @@ -135,6 +135,8 @@ static const struct hw_sequencer_funcs dcn35_funcs = { .update_dchubp_dpp = dcn20_update_dchubp_dpp, .post_unlock_reset_opp = dcn20_post_unlock_reset_opp, .get_underflow_debug_data = dcn30_get_underflow_debug_data, + .dmub_hw_control_lock = dcn35_dmub_hw_control_lock, + .dmub_hw_control_lock_fast = dcn35_dmub_hw_control_lock_fast, }; static const struct hwseq_private_funcs dcn35_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c index 19ec5b4edfdc..521b126d4736 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c @@ -124,6 +124,8 @@ static const struct hw_sequencer_funcs dcn351_funcs = { .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, .setup_hpo_hw_control = dcn35_setup_hpo_hw_control, .get_underflow_debug_data = dcn30_get_underflow_debug_data, + .dmub_hw_control_lock = dcn35_dmub_hw_control_lock, + .dmub_hw_control_lock_fast = dcn35_dmub_hw_control_lock_fast, }; static const struct hwseq_private_funcs dcn351_private_funcs = { -- 2.43.0
