From: Alvin Lee <[email protected]> [WHY] dcn60 uses dpp50_set_pregam_state, which reads PRE_GAM through the dcn50_dpp_registers layout. PRE_GAM sat at a different offset in dcn50 (based on DCN401) vs dcn60 (based on DCN42), so the cast landed on the wrong register which causes the wrong address to be used
[HOW] Rebase the DPP macro inheritance so PRE_GAM shares a common offset: DCN50 lists now inherit from DCN42, and DCN60 lists inherit from DCN50. The dcn60 struct layout is unchanged, so PRE_GAM aligns between the two and dpp50_set_pregam_state programs the correct address. Reviewed-by: Taimur Hassan <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Hung <[email protected]> --- drivers/gpu/drm/amd/display/dc/dpp/dcn50/dcn50_dpp.h | 11 ++++++----- drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.h | 7 ++----- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn50/dcn50_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn50/dcn50_dpp.h index efa76579dc9b..7f5d3fa6bbef 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn50/dcn50_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn50/dcn50_dpp.h @@ -11,28 +11,29 @@ #include "dcn30/dcn30_dpp.h" #include "dcn32/dcn32_dpp.h" #include "dcn401/dcn401_dpp.h" +#include "dcn42/dcn42_dpp.h" #define TO_DCN50_DPP(dpp)\ container_of(dpp, struct dcn50_dpp, base) #define DPP_REG_LIST_SH_MASK_DCN50_COMMON(mask_sh)\ - DPP_REG_LIST_SH_MASK_DCN401_COMMON(mask_sh), \ + DPP_REG_LIST_SH_MASK_DCN42_COMMON(mask_sh), \ TF_SF(CNVC_CFG0_PRE_GAM, PRE_GAM_MODE, mask_sh), \ TF_SF(CNVC_CFG0_PRE_GAM, PRE_DEGAM_SELECT, mask_sh), \ TF_SF(CNVC_CFG0_PRE_GAM, PRE_REGAM_SELECT, mask_sh) #define DPP_REG_FIELD_LIST_DCN50(type) \ - DPP_REG_FIELD_LIST_DCN401(type); \ + DPP_REG_FIELD_LIST_DCN42(type); \ type PRE_GAM_MODE; \ type PRE_REGAM_SELECT #define DPP_REG_VARIABLE_LIST_DCN50 \ - DPP_REG_VARIABLE_LIST_DCN401; \ - uint32_t PRE_GAM; + DPP_REG_VARIABLE_LIST_DCN42; \ + uint32_t PRE_GAM struct dcn50_dpp_registers { - DPP_REG_VARIABLE_LIST_DCN50 + DPP_REG_VARIABLE_LIST_DCN50; }; struct dcn50_dpp_shift { diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.h index 96ff26a5ed65..a0cc57e79ff7 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.h @@ -414,9 +414,7 @@ TF_SF(CNVC_CFG0_CNVC_UPSP_CLAMP, UPSP_CLAMP_MIN, mask_sh) #define DPP_REG_FIELD_LIST_DCN60(type) \ - DPP_REG_FIELD_LIST_DCN42(type); \ - type PRE_GAM_MODE; \ - type PRE_REGAM_SELECT; \ + DPP_REG_FIELD_LIST_DCN50(type); \ type AUTOCAL_FRAC_MODE; \ type SCL_BLACK_COLOR_RGB_Y; \ type SCL_BLACK_COLOR_CBCR; \ @@ -448,8 +446,7 @@ type UPSP_CLAMP_MIN #define DPP_REG_VARIABLE_LIST_DCN60 \ - DPP_REG_VARIABLE_LIST_DCN42; \ - uint32_t PRE_GAM; \ + DPP_REG_VARIABLE_LIST_DCN50; \ uint32_t SCL_BLACK_COLOR; \ uint32_t UPSP_MODE; \ uint32_t UPSP_V_COEF_P0; \ -- 2.43.0
