From: Tomasz Siemek <[email protected]> [WHY] Cursor SDR white level calculation is common across DCN generations and does not require an ASIC-specific HWSS implementation. Keeping it in the DCN10 HWSS extension duplicated generic policy in generation-specific code and made block sequence execution depend on mutable pipe context.
[HOW] Move cursor SDR white level calculation into dc_hw_sequencer. Store the calculated DPP cursor attributes in the block sequence so execution only invokes set_optional_cursor_attributes. Reviewed-by: Ilya Bakoulin <[email protected]> Signed-off-by: Tomasz Siemek <[email protected]> Signed-off-by: Alex Hung <[email protected]> --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 55 +++++++++++++------ .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 26 ++------- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 3 +- .../amd/display/dc/hwss/dcn50/dcn50_hwseq.c | 3 +- .../drm/amd/display/dc/hwss/hw_sequencer.h | 7 ++- 6 files changed, 51 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 1b9bcc3f0d2b..e40bad702f0f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3957,8 +3957,7 @@ static void program_cursor_attributes_sequence( hwss_add_set_cursor_attribute(seq_state, dc, tmp_pipe); if (dc->ctx->dmub_srv) hwss_add_send_update_cursor_info_to_dmu(seq_state, tmp_pipe, k); - if (dc->hwss.set_cursor_sdr_white_level) - hwss_add_set_cursor_sdr_white_level(seq_state, dc, tmp_pipe); + hwss_add_set_cursor_sdr_white_level(seq_state, tmp_pipe); if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) hwss_add_update_cursor_offload_pipe(seq_state, dc, tmp_pipe); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 47320ac01711..7ad30a1f2978 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -786,6 +786,29 @@ static void calc_vline_position( ASSERT(0); } +struct dpp_cursor_attributes calc_sdr_cursor_attributes(struct pipe_ctx *pipe_ctx) +{ + uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level; + struct fixed31_32 multiplier; + struct dpp_cursor_attributes opt_attr = { 0 }; + uint32_t hw_scale = 0x3c00; // 1.0 default multiplier + struct custom_float_format fmt; + + fmt.exponenta_bits = 5; + fmt.mantissa_bits = 10; + fmt.sign = true; + + if (sdr_white_level > 80) { + multiplier = dc_fixpt_from_fraction(sdr_white_level, 80); + convert_to_custom_float_format(multiplier, &fmt, &hw_scale); + } + + opt_attr.scale = hw_scale; + opt_attr.bias = 0; + + return opt_attr; +} + // Function to check if any update flags are set static bool get_pipe_update_bits_status(struct pipe_ctx *pipe, struct dc_plane_state *plane, struct dc_stream_state *stream) { @@ -1183,6 +1206,7 @@ void hwss_build_fast_sequence(struct dc *dc, struct pipe_ctx *current_mpc_pipe = NULL; bool is_dmub_lock_required = false; unsigned int i = 0; + struct block_sequence_state seq_state = { .steps = block_sequence, .num_steps = num_steps }; *num_steps = 0; // Initialize to 0 @@ -1341,11 +1365,7 @@ void hwss_build_fast_sequence(struct dc *dc, (*num_steps)++; } - block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.dc = dc; - block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = - current_pipe; - block_sequence[*num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL; - (*num_steps)++; + hwss_add_set_cursor_sdr_white_level(&seq_state, current_pipe); if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) { block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc; @@ -4385,11 +4405,10 @@ void hwss_set_cursor_position(union block_sequence_params *params) void hwss_set_cursor_sdr_white_level(union block_sequence_params *params) { - struct dc *dc = params->set_cursor_sdr_white_level_params.dc; - struct pipe_ctx *pipe_ctx = params->set_cursor_sdr_white_level_params.pipe_ctx; + struct dpp *dpp = params->set_cursor_sdr_white_level_params.dpp; - if (dc && dc->hwss.set_cursor_sdr_white_level) - dc->hwss.set_cursor_sdr_white_level(pipe_ctx); + if (dpp->funcs->set_optional_cursor_attributes) + dpp->funcs->set_optional_cursor_attributes(dpp, ¶ms->set_cursor_sdr_white_level_params.attr); } void hwss_program_gamut_remap(struct pipe_ctx *pipe_ctx) @@ -5771,15 +5790,19 @@ void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, } void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state, - struct dc *dc, struct pipe_ctx *pipe_ctx) { - if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { - seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL; - seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.dc = dc; - seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = pipe_ctx; - (*seq_state->num_steps)++; - } + struct dpp *dpp = pipe_ctx->plane_res.dpp; + struct dpp_cursor_attributes attr; + + if (dpp && dpp->funcs->set_optional_cursor_attributes) + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + attr = calc_sdr_cursor_attributes(pipe_ctx); + seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL; + seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.dpp = dpp; + seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.attr = attr; + (*seq_state->num_steps)++; + } } void hwss_add_program_output_csc(struct block_sequence_state *seq_state, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index b1679791f903..1b0fc0853045 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -3938,29 +3938,13 @@ void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx) void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx) { - uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level; - struct fixed31_32 multiplier; - struct dpp_cursor_attributes opt_attr = { 0 }; - uint32_t hw_scale = 0x3c00; // 1.0 default multiplier - struct custom_float_format fmt; - - if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes) - return; - - fmt.exponenta_bits = 5; - fmt.mantissa_bits = 10; - fmt.sign = true; + struct dpp *dpp = pipe_ctx->plane_res.dpp; + struct dpp_cursor_attributes attr; - if (sdr_white_level > 80) { - multiplier = dc_fixpt_from_fraction(sdr_white_level, 80); - convert_to_custom_float_format(multiplier, &fmt, &hw_scale); + if (dpp && dpp->funcs->set_optional_cursor_attributes) { + attr = calc_sdr_cursor_attributes(pipe_ctx); + dpp->funcs->set_optional_cursor_attributes(dpp, &attr); } - - opt_attr.scale = hw_scale; - opt_attr.bias = 0; - - pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes( - pipe_ctx->plane_res.dpp, &opt_attr); } /* diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 8e0ccc9d5819..7b089ae5c9c3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -3743,8 +3743,7 @@ void dcn401_update_dchubp_dpp_sequence(struct dc *dc, hwss_add_set_cursor_position(seq_state, dc, pipe_ctx); /* Step 16: Cursor SDR white level */ - if (dc->hwss.set_cursor_sdr_white_level) - hwss_add_set_cursor_sdr_white_level(seq_state, dc, pipe_ctx); + hwss_add_set_cursor_sdr_white_level(seq_state, pipe_ctx); } /* Step 17: Gamut remap and output CSC */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c index a7f8fd03faea..c13d1ad8d000 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c @@ -366,8 +366,7 @@ void dcn50_update_dchubp_dpp_sequence(struct dc *dc, hwss_add_set_cursor_position(seq_state, dc, pipe_ctx); /* Step 15: Cursor SDR white level */ - if (dc->hwss.set_cursor_sdr_white_level) - hwss_add_set_cursor_sdr_white_level(seq_state, dc, pipe_ctx); + hwss_add_set_cursor_sdr_white_level(seq_state, pipe_ctx); } /* Step 16: Gamut remap and output CSC */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 4f0d000eab94..83d9d699e929 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -872,8 +872,8 @@ struct set_cursor_position_params { }; struct set_cursor_sdr_white_level_params { - struct dc *dc; - struct pipe_ctx *pipe_ctx; + struct dpp *dpp; + struct dpp_cursor_attributes attr; }; struct program_output_csc_params { @@ -1802,6 +1802,8 @@ void set_drr_and_clear_adjust_pending( struct dc_stream_state *stream, struct drr_params *params); +struct dpp_cursor_attributes calc_sdr_cursor_attributes(struct pipe_ctx *pipe_ctx); + void hwss_execute_sequence(struct dc *dc, struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], int num_steps); @@ -2610,7 +2612,6 @@ void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, struct pipe_ctx *pipe_ctx); void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state, - struct dc *dc, struct pipe_ctx *pipe_ctx); void hwss_add_program_output_csc(struct block_sequence_state *seq_state, -- 2.43.0
