SMU 13.0.2 restores the default GFXCLK range by sending a frequency limit command and then clears the custom range. This bypasses the staged pp_od_clk_voltage transaction.
Stage the default GFXCLK range in the custom state instead. The existing PP_OD_COMMIT_DPM_TABLE path remains the sole PMFW update operation. Signed-off-by: Kevin Wang <[email protected]> --- .../gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index 1aa589bdc301..d07ad50d2666 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -1354,17 +1354,10 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_ dev_err(smu->adev->dev, "Input parameter number not correct\n"); return -EINVAL; } else { - /* Use the default frequencies for manual and determinism mode */ - min_clk = SMU_DPM_TABLE_MIN( - &dpm_context->dpm_tables.gfx_table); - max_clk = SMU_DPM_TABLE_MAX( - &dpm_context->dpm_tables.gfx_table); - - ret = aldebaran_set_soft_freq_limited_range( - smu, SMU_GFXCLK, min_clk, max_clk, false); - if (ret) - return ret; - smu_v13_0_reset_custom_level(smu); + pstate_table->gfxclk_pstate.custom.min = + SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table); + pstate_table->gfxclk_pstate.custom.max = + SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table); } break; case PP_OD_COMMIT_DPM_TABLE: -- 2.55.0
