gfx_v9_0_constants_init() programs SH_MEM_CONFIG and SH_MEM_BASES of VMID 0 and the kernel queue VMIDs, and gfx_v9_0_init_compute_vmid() those of the user queue VMIDs, each walking its own VMID mask.
Program them in one place, walking the kernel queue and the user queue VMIDs together and giving each the configuration of its users: the kernel queue VMIDs keep the retry mode of the GMC and the GPUVM apertures, VMID 0 null bases, and the user queue VMIDs the 64-bit address mode and the application apertures. The GDS, GWS and OA clearing of the user queue VMIDs in gfx_v9_0_init_compute_vmid() goes away, gfx_v9_0_init_gds_vmid() clears them for all VMIDs but 0 right after. No functional change. Suggested-by: Alex Deucher <[email protected]> Signed-off-by: Jesse Zhang <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 89 ++++++++++----------------- 1 file changed, 34 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 75d1bbdb421f..c02777f9137e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2584,42 +2584,54 @@ static void gfx_v9_0_debug_trap_config_init(struct amdgpu_device *adev, } #define DEFAULT_SH_MEM_BASES (0x6000) -static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) +/* + * Program SH_MEM_CONFIG and SH_MEM_BASES of all VMIDs in one place: the user + * queue VMIDs get the 64-bit address mode and the application apertures, + * VMID 0 and the kernel queue VMIDs, including the SPM VMID, the retry mode + * of the GMC, the kernel queue VMIDs the GPUVM apertures and VMID 0 null + * bases. + */ +static void gfx_v9_0_init_sh_mem(struct amdgpu_device *adev) { + unsigned long uq_mask = adev->vm_manager.vmid_uq_mask_gfxhub; + unsigned long mask = amdgpu_vmid_kq_mask(adev, AMDGPU_GFXHUB(0)) | uq_mask; + u32 kq_config, kq_bases, uq_config, uq_bases; int i; - uint32_t sh_mem_config; - uint32_t sh_mem_bases; + + kq_config = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); + kq_config = REG_SET_FIELD(kq_config, SH_MEM_CONFIG, RETRY_DISABLE, + !!adev->gmc.noretry); + kq_bases = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, + adev->gmc.private_aperture_start >> 48); + kq_bases = REG_SET_FIELD(kq_bases, SH_MEM_BASES, SHARED_BASE, + adev->gmc.shared_aperture_start >> 48); /* - * Configure apertures: + * Configure apertures of the user queue VMIDs: * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) */ - sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); - - sh_mem_config = SH_MEM_ADDRESS_MODE_64 | - SH_MEM_ALIGNMENT_MODE_UNALIGNED << - SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; + uq_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); + uq_config = SH_MEM_ADDRESS_MODE_64 | + SH_MEM_ALIGNMENT_MODE_UNALIGNED << + SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; mutex_lock(&adev->srbm_mutex); - for_each_uq_gfx_vmid(i, adev) { + for_each_set_bit(i, &mask, AMDGPU_NUM_VMID) { soc15_grbm_select(adev, 0, 0, 0, i, 0); /* CP and shaders */ - WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); - WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); + if (uq_mask & BIT(i)) { + WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, uq_config); + WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, uq_bases); + } else { + WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, kq_config); + WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, i ? kq_bases : 0); + } } soc15_grbm_select(adev, 0, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); - - /* Initialize all compute VMIDs to have no GDS, GWS, or OA - access. These should be enabled by FW for target VMIDs. */ - for_each_uq_gfx_vmid(i, adev) { - WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); - WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); - WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); - WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); - } } static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) @@ -2661,9 +2673,6 @@ static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) static void gfx_v9_0_constants_init(struct amdgpu_device *adev) { - u32 tmp; - int i; - if (!amdgpu_sriov_vf(adev) || amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 2)) { WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); @@ -2676,37 +2685,7 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev) gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); - /* XXX SH_MEM regs */ - /* where to put LDS, scratch, GPUVM in FSA64 space */ - mutex_lock(&adev->srbm_mutex); - for_each_vmid_and_zero(i, adev, AMDGPU_GFXHUB(0)) { - soc15_grbm_select(adev, 0, 0, 0, i, 0); - /* CP and shaders */ - if (i == 0) { - tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, - SH_MEM_ALIGNMENT_MODE_UNALIGNED); - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, - !!adev->gmc.noretry); - WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); - WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); - } else { - tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, - SH_MEM_ALIGNMENT_MODE_UNALIGNED); - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, - !!adev->gmc.noretry); - WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); - tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, - (adev->gmc.private_aperture_start >> 48)); - tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, - (adev->gmc.shared_aperture_start >> 48)); - WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); - } - } - soc15_grbm_select(adev, 0, 0, 0, 0, 0); - - mutex_unlock(&adev->srbm_mutex); - - gfx_v9_0_init_compute_vmid(adev); + gfx_v9_0_init_sh_mem(adev); gfx_v9_0_init_gds_vmid(adev); gfx_v9_0_init_sq_config(adev); } -- 2.50.1
