gfx_v10_0_constants_init() programs SH_MEM_CONFIG and SH_MEM_BASES of VMID 0 and the kernel queue VMIDs, and gfx_v10_0_init_compute_vmid() those of the user queue VMIDs, each walking its own VMID mask.
Program them in one place, walking the kernel queue and the user queue VMIDs together and giving each the configuration of its users, as on GFX11 and GFX12, and keep enabling the traps of the user queue VMIDs with gfx_v10_0_debug_trap_config_init(). The GDS, GWS and OA clearing of the user queue VMIDs in gfx_v10_0_init_compute_vmid() goes away, gfx_v10_0_init_gds_vmid() clears them for all VMIDs but 0 right after. No functional change. Suggested-by: Alex Deucher <[email protected]> Signed-off-by: Jesse Zhang <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 65 ++++++++++---------------- 1 file changed, 24 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index b6f61f4a08e5..c48099f62133 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -5193,41 +5193,46 @@ static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); } -static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) +/* + * Program SH_MEM_CONFIG and SH_MEM_BASES of all VMIDs in one place: the user + * queue VMIDs get the application apertures and traps enabled, the kernel + * queue VMIDs, including the SPM VMID, the GPUVM apertures. VMID 0 only gets + * SH_MEM_CONFIG, its SH_MEM_BASES is left alone. + */ +static void gfx_v10_0_init_sh_mem(struct amdgpu_device *adev) { + unsigned long uq_mask = adev->vm_manager.vmid_uq_mask_gfxhub; + unsigned long mask = amdgpu_vmid_kq_mask(adev, AMDGPU_GFXHUB(0)) | uq_mask; + u32 kq_bases, uq_bases; int i; - uint32_t sh_mem_bases; + + kq_bases = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, + adev->gmc.private_aperture_start >> 48); + kq_bases = REG_SET_FIELD(kq_bases, SH_MEM_BASES, SHARED_BASE, + adev->gmc.shared_aperture_start >> 48); /* - * Configure apertures: + * Configure apertures of the user queue VMIDs: * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) */ - sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); + uq_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); mutex_lock(&adev->srbm_mutex); - for_each_uq_gfx_vmid(i, adev) { + for_each_set_bit(i, &mask, AMDGPU_NUM_VMID) { nv_grbm_select(adev, 0, 0, 0, i); /* CP and shaders */ WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); - WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); + if (uq_mask & BIT(i)) + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, uq_bases); + else if (i) + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, kq_bases); } nv_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); - /* - * Initialize all compute VMIDs to have no GDS, GWS, or OA - * access. These should be enabled by FW for target VMIDs. - */ - for_each_uq_gfx_vmid(i, adev) { - WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); - WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); - WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); - WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); - } - - gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.vmid_uq_mask_gfxhub); + gfx_v10_0_debug_trap_config_init(adev, uq_mask); } static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) @@ -5336,9 +5341,6 @@ static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) static void gfx_v10_0_constants_init(struct amdgpu_device *adev) { - u32 tmp; - int i; - if (!amdgpu_sriov_vf(adev)) WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); @@ -5357,26 +5359,7 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) WREG32_FIELD15(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL, (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1); - /* XXX SH_MEM regs */ - /* where to put LDS, scratch, GPUVM in FSA64 space */ - mutex_lock(&adev->srbm_mutex); - for_each_vmid_and_zero(i, adev, AMDGPU_GFXHUB(0)) { - nv_grbm_select(adev, 0, 0, 0, i); - /* CP and shaders */ - WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); - if (i != 0) { - tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, - (adev->gmc.private_aperture_start >> 48)); - tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, - (adev->gmc.shared_aperture_start >> 48)); - WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); - } - } - nv_grbm_select(adev, 0, 0, 0, 0); - - mutex_unlock(&adev->srbm_mutex); - - gfx_v10_0_init_compute_vmid(adev); + gfx_v10_0_init_sh_mem(adev); gfx_v10_0_init_gds_vmid(adev); } -- 2.50.1
