Some platforms ship BIOS with either a default or an alternative trust authority, so firmware for every IP must be signed with the matching scheme. The PSP advertises which one is in use in bit 6 of C2PMSG_63, and in bit 28 whether this is a preproduction part, which needs firmware of its own.
Add amdgpu_psp_init_fw_variant() which reads those bits through amdgpu's own MMIO, and keep the result in adev->firmware.sign_type and adev->firmware.preprod next to load_type. It is initialized once, after IP discovery has populated the register bases and only when firmware is loaded through the front door (the PSP). Only MP0 15.0.0 reports it. For all other ASICs, SR-IOV VFs and an inaccessible register (all ones) the defaults are kept: AMDGPU_FW_SIGN_DEFAULT and not preproduction. A preproduction part that also reports the alternative scheme is not expected, so warn about it and use the default firmware. Firmware for preproduction parts is named with a "_p" suffix before the extension and firmware for the alternative scheme with an "_l" suffix (e.g. "foo.bin" becomes "foo_p.bin" or "foo_l.bin"). Production parts on the default scheme use the plain names. Do the substitution centrally in amdgpu_ucode_request() so it covers every IP that loads firmware through it (PSP, SMU, DMUB, GC, IMU, MES, SDMA, VCN, VPE, ...) without each loader having to care. There is no fallback to the default file: it would be rejected anyway. Declare the variants of the Medusa IPs with MODULE_FIRMWARE() so that initramfs generators include them. Signed-off-by: Mario Limonciello <[email protected]> --- v2: * Cover PSP 15.0.9 too. * Cover MODULE_FIRMWARE declarations for more files. --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 32 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 25 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 7 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 16 ++++++++ drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 4 ++ drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 ++ drivers/gpu/drm/amd/amdgpu/psp_v15_0.c | 37 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/psp_v15_0.h | 1 + drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 2 + drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c | 2 + .../amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 2 + .../amd/display/amdgpu_dm/amdgpu_dm_dmub.h | 2 + 15 files changed, 143 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index c170bf3b61281..799a76e1cfe77 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2098,6 +2098,10 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) amdgpu_ip_version((adev), GC_HWIP, 0) == IP_VERSION(9, 4, 4); } + /* Needs the register bases, and must be known before requesting firmware */ + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) + amdgpu_psp_init_fw_variant(adev); + total = true; for (i = 0; i < adev->num_ip_blocks; i++) { ip_block = &adev->ip_blocks[i]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index c0ed3e24b6840..4f060666f12a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -403,6 +403,38 @@ static uint64_t psp_get_runtime_db_header_pos(struct amdgpu_device *adev) return pos; } +/* + * Which firmware the platform needs, as reported by the PSP in C2PMSG_63: the + * signing scheme and whether this is a preproduction part. The defaults are kept if + * the ASIC doesn't report it or it can't be read. + */ +void amdgpu_psp_init_fw_variant(struct amdgpu_device *adev) +{ + bool alt, preprod; + + if (amdgpu_sriov_vf(adev)) + return; + + switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { + case IP_VERSION(15, 0, 0): + case IP_VERSION(15, 0, 9): + if (psp_v15_0_0_get_fw_variant(adev, &alt, &preprod)) + return; + break; + default: + return; + } + + if (alt && preprod) { + drm_warn(adev_to_drm(adev), + "Preproduction part with alternative signing, using default firmware\n"); + return; + } + + adev->firmware.sign_type = alt ? AMDGPU_FW_SIGN_ALT : AMDGPU_FW_SIGN_DEFAULT; + adev->firmware.preprod = preprod; +} + /* * Helper funciton to query psp runtime database entry * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 975d123593588..9b04e51f589ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -631,6 +631,7 @@ int psp_ta_invoke(struct psp_context *psp, int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); bool psp_is_xgmi_ta_supported(struct psp_context *psp); +void amdgpu_psp_init_fw_variant(struct amdgpu_device *adev); int psp_xgmi_terminate(struct psp_context *psp); int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index d2ce526dd95cc..eeb056dcad2c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -1527,6 +1527,27 @@ void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev); } +/* Add the suffix of the firmware variant before the extension: foo.bin -> foo_l.bin */ +static int amdgpu_ucode_set_suffix(struct amdgpu_device *adev, char *fname, size_t size) +{ + const char *suffix = ".bin"; + size_t len = strlen(fname), base; + + if (adev->firmware.preprod) + suffix = "_p.bin"; + else if (adev->firmware.sign_type == AMDGPU_FW_SIGN_ALT) + suffix = "_l.bin"; + + if (len < strlen(".bin") || strcmp(fname + len - strlen(".bin"), ".bin")) + return 0; + + base = len - strlen(".bin"); + if (strscpy(fname + base, suffix, size - base) < 0) + return -EOVERFLOW; + + return 0; +} + /* * amdgpu_ucode_request - Fetch and validate amdgpu microcode * @@ -1555,6 +1576,10 @@ int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, return -EOVERFLOW; } + r = amdgpu_ucode_set_suffix(adev, fname, sizeof(fname)); + if (r) + return r; + if (required == AMDGPU_UCODE_REQUIRED) r = request_firmware(fw, fname, adev->dev); else { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index 7c809692807fc..a77758c07be23 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -571,6 +571,11 @@ enum amdgpu_firmware_load_type { AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, }; +enum amdgpu_firmware_sign_type { + AMDGPU_FW_SIGN_DEFAULT = 0, + AMDGPU_FW_SIGN_ALT, +}; + enum amdgpu_ucode_required { AMDGPU_UCODE_OPTIONAL, AMDGPU_UCODE_REQUIRED, @@ -606,6 +611,8 @@ struct amdgpu_firmware_info { struct amdgpu_firmware { struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; enum amdgpu_firmware_load_type load_type; + enum amdgpu_firmware_sign_type sign_type; + bool preprod; struct amdgpu_bo *fw_buf; unsigned int fw_size; unsigned int max_ucodes; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 6c12d8aa3c769..1df2725d31e0c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -66,6 +66,8 @@ #define FIRMWARE_VCN5_0_1 "amdgpu/vcn_5_0_1.bin" #define FIRMWARE_VCN5_0_2 "amdgpu/vcn_5_0_2.bin" #define FIRMWARE_VCN5_3_0 "amdgpu/vcn_5_3_0.bin" +#define FIRMWARE_VCN5_3_0_ALT "amdgpu/vcn_5_3_0_l.bin" +#define FIRMWARE_VCN5_3_0_PREPROD "amdgpu/vcn_5_3_0_p.bin" MODULE_FIRMWARE(FIRMWARE_RAVEN); MODULE_FIRMWARE(FIRMWARE_PICASSO); @@ -95,6 +97,8 @@ MODULE_FIRMWARE(FIRMWARE_VCN5_0_0); MODULE_FIRMWARE(FIRMWARE_VCN5_0_1); MODULE_FIRMWARE(FIRMWARE_VCN5_0_2); MODULE_FIRMWARE(FIRMWARE_VCN5_3_0); +MODULE_FIRMWARE(FIRMWARE_VCN5_3_0_ALT); +MODULE_FIRMWARE(FIRMWARE_VCN5_3_0_PREPROD); static void amdgpu_vcn_idle_work_handler(struct work_struct *work); static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 5d068a9d9c72c..3d82cfbd14f17 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -134,13 +134,29 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_6_me.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_6_mec.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_6_rlc.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_0_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_pfp_l.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_pfp_p.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_0_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_me_l.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_me_p.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_0_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_mec_l.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_mec_p.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_0_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_rlc_l.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_rlc_p.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_1_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_1_pfp_l.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_1_pfp_p.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_1_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_1_me_l.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_1_me_p.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_1_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_1_mec_l.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_1_mec_p.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_1_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_1_rlc_l.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_1_rlc_p.bin"); static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = { SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c index 09dc01a425d13..a409911939d38 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c @@ -44,7 +44,11 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_3_imu.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_4_imu.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_6_imu.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_0_imu.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_imu_l.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_imu_p.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_1_imu.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_1_imu_l.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_1_imu_p.bin"); static int imu_v11_0_init_microcode(struct amdgpu_device *adev) { diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 60b27278a598b..e9778f950738a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -61,7 +61,11 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes1.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes_2.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes1.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes_2.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes_2_l.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes_2_p.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes1.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes1_l.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes1_p.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes_2.bin"); MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes1.bin"); diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c index abaa40b6def90..148d62e68225b 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c @@ -32,11 +32,19 @@ #include "mp/mp_15_0_0_sh_mask.h" MODULE_FIRMWARE("amdgpu/psp_15_0_0_toc.bin"); +MODULE_FIRMWARE("amdgpu/psp_15_0_0_toc_l.bin"); +MODULE_FIRMWARE("amdgpu/psp_15_0_0_toc_p.bin"); MODULE_FIRMWARE("amdgpu/psp_15_0_0_ta.bin"); +MODULE_FIRMWARE("amdgpu/psp_15_0_0_ta_l.bin"); +MODULE_FIRMWARE("amdgpu/psp_15_0_0_ta_p.bin"); MODULE_FIRMWARE("amdgpu/psp_15_0_5_toc.bin"); MODULE_FIRMWARE("amdgpu/psp_15_0_5_ta.bin"); MODULE_FIRMWARE("amdgpu/psp_15_0_9_toc.bin"); +MODULE_FIRMWARE("amdgpu/psp_15_0_9_toc_l.bin"); +MODULE_FIRMWARE("amdgpu/psp_15_0_9_toc_p.bin"); MODULE_FIRMWARE("amdgpu/psp_15_0_9_ta.bin"); +MODULE_FIRMWARE("amdgpu/psp_15_0_9_ta_l.bin"); +MODULE_FIRMWARE("amdgpu/psp_15_0_9_ta_p.bin"); #define regMPASP_PCRU0_MPASP_C2PMSG_64 0x4280 #define regMPASP_PCRU0_MPASP_C2PMSG_64_BASE_IDX 2 @@ -108,6 +116,35 @@ static int psp_v15_0_0_ring_stop(struct psp_context *psp, return ret; } +/* + * C2PMSG_63 bit 6: 0 = default firmware signing, 1 = alternative + * C2PMSG_63 bit 28: 0 = production part, 1 = preproduction part + */ +#define PSP_V15_0_0_FW_SIGN_ALT BIT(6) +#define PSP_V15_0_0_FW_PREPROD BIT(28) + +int psp_v15_0_0_get_fw_variant(struct amdgpu_device *adev, bool *alt, bool *preprod) +{ + u32 val; + + if (!adev->reg_offset[MP0_HWIP][0]) + return -ENODEV; + + val = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_63); + if (val == 0xffffffff) { + drm_warn(adev_to_drm(adev), "Unable to access regMPASP_SMN_C2PMSG_63\n"); + return -EIO; + } + + *alt = !!(val & PSP_V15_0_0_FW_SIGN_ALT); + *preprod = !!(val & PSP_V15_0_0_FW_PREPROD); + dev_info(adev->dev, "PSP firmware: %s signing, %s part (C2PMSG_63=0x%08x)\n", + *alt ? "alternative" : "default", + *preprod ? "preproduction" : "production", val); + + return 0; +} + static int psp_v15_0_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type) { diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.h index ebd612103526f..2915ddcfff312 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.h @@ -26,5 +26,6 @@ #include "amdgpu_psp.h" void psp_v15_0_0_set_psp_funcs(struct psp_context *psp); +int psp_v15_0_0_get_fw_variant(struct amdgpu_device *adev, bool *alt, bool *preprod); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 4845588c4c247..2586d49f1e940 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -56,6 +56,8 @@ MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin"); MODULE_FIRMWARE("amdgpu/sdma_6_1_2.bin"); MODULE_FIRMWARE("amdgpu/sdma_6_1_3.bin"); MODULE_FIRMWARE("amdgpu/sdma_6_1_4.bin"); +MODULE_FIRMWARE("amdgpu/sdma_6_1_4_l.bin"); +MODULE_FIRMWARE("amdgpu/sdma_6_1_4_p.bin"); MODULE_FIRMWARE("amdgpu/sdma_6_4_0.bin"); #define SDMA1_REG_OFFSET 0x600 diff --git a/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c index c92c5fc59aeb9..cefb8d739faf8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c @@ -31,6 +31,8 @@ #include "vpe/vpe_2_0_0_sh_mask.h" MODULE_FIRMWARE("amdgpu/vpe_2_0_0.bin"); +MODULE_FIRMWARE("amdgpu/vpe_2_0_0_l.bin"); +MODULE_FIRMWARE("amdgpu/vpe_2_0_0_p.bin"); MODULE_FIRMWARE("amdgpu/vpe_2_2_0.bin"); #define VPE_THREAD1_UCODE_OFFSET 0x8000 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c index 0ea8f9a582ccc..b28d67b4e70aa 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c @@ -62,6 +62,8 @@ MODULE_FIRMWARE(FIRMWARE_DCN_351_DMUB); MODULE_FIRMWARE(FIRMWARE_DCN_36_DMUB); MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB); MODULE_FIRMWARE(FIRMWARE_DCN_42_DMUB); +MODULE_FIRMWARE(FIRMWARE_DCN_42_DMUB_ALT); +MODULE_FIRMWARE(FIRMWARE_DCN_42_DMUB_PREPROD); MODULE_FIRMWARE(FIRMWARE_DCN_42B_DMUB); MODULE_FIRMWARE(FIRMWARE_DCN_60_DMUB); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.h index df3e776c1ad14..219e9c0427441 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.h @@ -61,6 +61,8 @@ int dm_init_microcode(struct amdgpu_device *adev); #define FIRMWARE_DCN_36_DMUB "amdgpu/dcn_3_6_dmcub.bin" #define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin" #define FIRMWARE_DCN_42_DMUB "amdgpu/dcn_4_2_dmcub.bin" +#define FIRMWARE_DCN_42_DMUB_ALT "amdgpu/dcn_4_2_dmcub_l.bin" +#define FIRMWARE_DCN_42_DMUB_PREPROD "amdgpu/dcn_4_2_dmcub_p.bin" #define FIRMWARE_DCN_42B_DMUB "amdgpu/dcn_4_2_1_dmcub.bin" #define FIRMWARE_DCN_60_DMUB "amdgpu/dcn_6_0_0_dmcub.bin" #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" -- 2.56.0
