From: Xiaojie Yuan <xiaojie.y...@amd.com>
Not used yet.
Signed-off-by: Xiaojie Yuan <xiaojie.y...@amd.com>
Reviewed-by: Hawking Zhang <hawking.zh...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 99b57537f867..dcce5e056c15 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -170,6 +170,11 @@ static const struct soc15_reg_golden
golden_settings_gc_10_1_nv14[] =
/* Pending on emulation bring up */
};
+static const struct soc15_reg_golden golden_settings_gc_10_1_nv12[] =
+{
+ /* Pending on emulation bring up */
+};
+
#define DEFAULT_SH_MEM_CONFIG \
((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -319,6 +324,14 @@ static void gfx_v10_0_init_golden_registers(struct
amdgpu_device *adev)
golden_settings_gc_10_1_nv14,
(const
u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
break;
+ case CHIP_NAVI12:
+ soc15_program_register_sequence(adev,
+ golden_settings_gc_10_1,
+ (const
u32)ARRAY_SIZE(golden_settings_gc_10_1));
+ soc15_program_register_sequence(adev,
+ golden_settings_gc_10_1_nv12,
+ (const
u32)ARRAY_SIZE(golden_settings_gc_10_1_nv12));
+ break;
default:
break;
}
--
2.20.1
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