From: Xiaojie Yuan <xiaojie.y...@amd.com>
Same as other navi asics.
Signed-off-by: Xiaojie Yuan <xiaojie.y...@amd.com>
Reviewed-by: Hawking Zhang <hawking.zh...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index a0bd14e9b8fe..4e3ac1084a94 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -525,6 +525,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
+ case CHIP_NAVI12:
default:
adev->gmc.gart_size = 512ULL << 20;
break;
@@ -603,10 +604,11 @@ static int gmc_v10_0_sw_init(void *handle)
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
+ case CHIP_NAVI12:
adev->num_vmhubs = 2;
/*
* To fulfill 4-level page support,
- * vm size is 256TB (48bit), maximum size of Navi10/Navi14,
+ * vm size is 256TB (48bit), maximum size of
Navi10/Navi14/Navi12,
* block size 512 (9bit)
*/
amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
@@ -721,6 +723,7 @@ static void gmc_v10_0_init_golden_registers(struct
amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
+ case CHIP_NAVI12:
break;
default:
break;
--
2.20.1
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