Add mc register table initialization.
Change-Id: I38a17c2f2747e5ef736c5dc55a84ee4e34d114b8
Signed-off-by: Evan Quan <evan.q...@amd.com>
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
---
.../drm/amd/pm/powerplay/hwmgr/ppatomctrl.c | 37 +++++++++++++++++++
.../drm/amd/pm/powerplay/hwmgr/ppatomctrl.h | 1 +
.../pm/powerplay/smumgr/polaris10_smumgr.c | 19 ++++++++++
.../pm/powerplay/smumgr/polaris10_smumgr.h | 1 +
4 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
index 3aaf2d64cd98..0d8a693b77e0 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
@@ -166,6 +166,43 @@ int atomctrl_initialize_mc_reg_table(
return result;
}
+int atomctrl_initialize_mc_reg_table_v2_2(
+ struct pp_hwmgr *hwmgr,
+ uint8_t module_index,
+ pp_atomctrl_mc_reg_table *table)
+{
+ ATOM_VRAM_INFO_HEADER_V2_2 *vram_info;
+ ATOM_INIT_REG_BLOCK *reg_block;
+ int result = 0;
+ u8 frev, crev;
+ u16 size;
+
+ vram_info = (ATOM_VRAM_INFO_HEADER_V2_2 *)
+ smu_atom_get_data_table(hwmgr->adev,
+ GetIndexIntoMasterTable(DATA, VRAM_Info),
&size, &frev, &crev);
+
+ if (module_index >= vram_info->ucNumOfVRAMModule) {
+ pr_err("Invalid VramInfo table.");
+ result = -1;
+ } else if (vram_info->sHeader.ucTableFormatRevision < 2) {
+ pr_err("Invalid VramInfo table.");
+ result = -1;
+ }
+
+ if (0 == result) {
+ reg_block = (ATOM_INIT_REG_BLOCK *)
+ ((uint8_t *)vram_info +
le16_to_cpu(vram_info->usMemClkPatchTblOffset));
+ result = atomctrl_set_mc_reg_address_table(reg_block, table);
+ }
+
+ if (0 == result) {
+ result = atomctrl_retrieve_ac_timing(module_index,
+ reg_block, table);
+ }
+
+ return result;
+}
+
/**
* Set DRAM timings based on engine clock and memory clock.
*/
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
index c6276ab073b7..3ef3ccfa6aa7 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
@@ -299,6 +299,7 @@ extern uint32_t atomctrl_get_mpll_reference_clock(struct
pp_hwmgr *hwmgr);
extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr,
const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr,
const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t
module_index, pp_atomctrl_mc_reg_table *table);
+extern int atomctrl_initialize_mc_reg_table_v2_2(struct pp_hwmgr *hwmgr,
uint8_t module_index, pp_atomctrl_mc_reg_table *table);
extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr,
uint32_t engine_clock, uint32_t memory_clock);
extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr,
uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool
strobe_mode);
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
index fad6ffb470ba..c4590a43a4f7 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
@@ -2522,6 +2522,24 @@ static int polaris10_process_firmware_header(struct
pp_hwmgr *hwmgr)
return error ? -1 : 0;
}
+static uint8_t polaris10_get_memory_modile_index(struct pp_hwmgr *hwmgr)
+{
+ return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device,
mmBIOS_SCRATCH_4) >> 16));
+}
+
+static int polaris10_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ struct polaris10_smumgr *smu_data = (struct polaris10_smumgr
*)(hwmgr->smu_backend);
+ pp_atomctrl_mc_reg_table *mc_reg_table = &smu_data->mc_reg_table;
+ uint8_t module_index = polaris10_get_memory_modile_index(hwmgr);
+
+ memset(mc_reg_table, 0, sizeof(pp_atomctrl_mc_reg_table));
+ result = atomctrl_initialize_mc_reg_table_v2_2(hwmgr, module_index,
mc_reg_table);
+
+ return result;
+}
+
static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
{
return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
@@ -2648,6 +2666,7 @@ const struct pp_smumgr_func polaris10_smu_funcs = {
.populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
.populate_all_memory_levels = polaris10_populate_all_memory_levels,
.get_mac_definition = polaris10_get_mac_definition,
+ .initialize_mc_reg_table = polaris10_initialize_mc_reg_table,
.is_dpm_running = polaris10_is_dpm_running,
.is_hw_avfs_present = polaris10_is_hw_avfs_present,
.update_dpm_settings = polaris10_update_dpm_settings,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h
b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h
index 1ec425df9eda..6f4c48ac34b8 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h
@@ -60,6 +60,7 @@ struct polaris10_smumgr {
struct polaris10_range_table range_table[NUM_SCLK_RANGE];
const struct polaris10_pt_defaults *power_tune_defaults;
uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK];
+ pp_atomctrl_mc_reg_table mc_reg_table;
};
--
2.28.0
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