Correct Polaris10 vddc phase control.
Change-Id: I182bc46adb7900cad243eb3906450d86ae41975e
Signed-off-by: Evan Quan <evan.q...@amd.com>
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
---
.../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 31 +++++++++++--------
.../pm/powerplay/smumgr/polaris10_smumgr.c | 7 ++++-
2 files changed, 24 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 03a139f2c426..79dea9329b2a 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -1664,6 +1664,8 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct amdgpu_device *adev = hwmgr->adev;
+ uint8_t tmp1, tmp2;
+ uint16_t tmp3 = 0;
data->dll_default_on = false;
data->mclk_dpm0_activity_target = 0xa;
@@ -1712,19 +1714,6 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr
*hwmgr)
hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
- if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
- uint8_t tmp1, tmp2;
- uint16_t tmp3 = 0;
- atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
- &tmp3);
- tmp3 = (tmp3 >> 5) & 0x3;
- data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) &
0x3;
- } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
- data->vddc_phase_shed_control = 1;
- } else {
- data->vddc_phase_shed_control = 0;
- }
-
if (hwmgr->chip_id == CHIP_HAWAII) {
data->thermal_temp_setting.temperature_low = 94500;
data->thermal_temp_setting.temperature_high = 95000;
@@ -1783,6 +1772,22 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr
*hwmgr)
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ControlVDDCI);
+ data->vddc_phase_shed_control = 1;
+ if ((hwmgr->chip_id == CHIP_POLARIS12) ||
+ ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
+ ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
+ ASICID_IS_P30(adev->pdev->device, adev->pdev->revision) ||
+ ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
+ if (data->voltage_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
+ atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1,
&tmp2,
+ &tmp3);
+ tmp3 = (tmp3 >> 5) & 0x3;
+ data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >>
1)) & 0x3;
+ }
+ } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
+ data->vddc_phase_shed_control = 1;
+ }
+
if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask &
PP_CLOCK_STRETCH_MASK)
&& (table_info->cac_dtp_table->usClockStretchAmount != 0))
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
index 46c82bfa793c..72ca4bd2c2f3 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
@@ -779,6 +779,7 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr
*hwmgr,
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct amdgpu_device *adev = hwmgr->adev;
state->CcPwrDynRm = 0;
state->CcPwrDynRm1 = 0;
@@ -787,7 +788,11 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr
*hwmgr,
state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
- if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker)
+ if ((hwmgr->chip_id == CHIP_POLARIS12) ||
+ ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
+ ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
+ ASICID_IS_P30(adev->pdev->device, adev->pdev->revision) ||
+ ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
else
state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
--
2.28.0
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