[PATCH] drm/amdgpu: Clean up errors in smu7_powertune.c

Ran Sun Tue, 01 Aug 2023 01:27:55 -0700

Fix the following errors reported by checkpatch:

ERROR: that open brace { should be on the previous line
ERROR: space required after that ',' (ctx:VxV)


Signed-off-by: Ran Sun <sunran...@208suo.com>
---
 .../gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
index 21be23ec3c79..edab3ef09d33 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
@@ -520,8 +520,7 @@ static const struct gpu_pt_config_reg 
DIDTConfig_Polaris12[] = {
        {   0xFFFFFFFF  }
 };
 
-static const struct gpu_pt_config_reg DIDTConfig_Polaris11_Kicker[] =
-{
+static const struct gpu_pt_config_reg DIDTConfig_Polaris11_Kicker[] = {
 /* 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  *      Offset                             Mask                                
                Shift                                               Value       
Type
  * 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -646,7 +645,7 @@ static const struct gpu_pt_config_reg 
DIDTConfig_Polaris11_Kicker[] =
        {   ixDIDT_TCP_STALL_CTRL,             
DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK,   
DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001,     
GPU_CONFIGREG_DIDT_IND },
        {   ixDIDT_TCP_STALL_CTRL,             
DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,      
DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,    0x0001,     
GPU_CONFIGREG_DIDT_IND },
        {   ixDIDT_TCP_STALL_CTRL,             
DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,      
DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,    0x0001,     
GPU_CONFIGREG_DIDT_IND },
-       {   ixDIDT_TCP_STALL_CTRL,             
DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK,  
DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT,0x01aa,     
GPU_CONFIGREG_DIDT_IND },
+       {   ixDIDT_TCP_STALL_CTRL,             
DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK,  
DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa,     
GPU_CONFIGREG_DIDT_IND },
        {   ixDIDT_TCP_STALL_CTRL,             
DIDT_TCP_STALL_CTRL__UNUSED_0_MASK,                 
DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT,               0x0000,     
GPU_CONFIGREG_DIDT_IND },
 
        {   ixDIDT_TCP_TUNING_CTRL,            
DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK,      
DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT,    0x0001,     
GPU_CONFIGREG_DIDT_IND },
@@ -666,8 +665,7 @@ static const struct gpu_pt_config_reg 
DIDTConfig_Polaris11_Kicker[] =
        {   0xFFFFFFFF  }  /* End of list */
 };
 
-static const struct gpu_pt_config_reg GCCACConfig_VegaM[] =
-{
+static const struct gpu_pt_config_reg GCCACConfig_VegaM[] = {
 // 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 //      Offset                             Mask                                
                Shift                                               Value       
Type
 // 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -703,8 +701,7 @@ static const struct gpu_pt_config_reg GCCACConfig_VegaM[] =
     {   0xFFFFFFFF  }  // End of list
 };
 
-static const struct gpu_pt_config_reg DIDTConfig_VegaM[] =
-{
+static const struct gpu_pt_config_reg DIDTConfig_VegaM[] = {
 // 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 //      Offset                             Mask                                
                Shift                                               Value       
Type
 // 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -831,7 +828,7 @@ static const struct gpu_pt_config_reg DIDTConfig_VegaM[] =
     {   ixDIDT_TCP_STALL_CTRL,             
DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK,   
DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001,     
GPU_CONFIGREG_DIDT_IND },
     {   ixDIDT_TCP_STALL_CTRL,             
DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,      
DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,    0x0001,     
GPU_CONFIGREG_DIDT_IND },
     {   ixDIDT_TCP_STALL_CTRL,             
DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,      
DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,    0x0001,     
GPU_CONFIGREG_DIDT_IND },
-    {   ixDIDT_TCP_STALL_CTRL,             
DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK,  
DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT,0x01aa,     
GPU_CONFIGREG_DIDT_IND },
+    {   ixDIDT_TCP_STALL_CTRL,             
DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK,  
DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x01aa,     
GPU_CONFIGREG_DIDT_IND },
     {   ixDIDT_TCP_STALL_CTRL,             DIDT_TCP_STALL_CTRL__UNUSED_0_MASK, 
                DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT,               0x0000,     
GPU_CONFIGREG_DIDT_IND },
 
     {   ixDIDT_TCP_TUNING_CTRL,            
DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK,      
DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT,    0x0001,     
GPU_CONFIGREG_DIDT_IND },
-- 
2.17.1

[PATCH] drm/amdgpu: Clean up errors in smu7_powertune.c

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