Hello Matthias & All: Would you be ready to replace the autogenerated readflashcell / writeflashcell code in device.asm for 128KB architectures as follows:
- clr temp7 - lsl zl - rol zh - rol temp7 - out_ RAMPZ, temp7 - elpm @0, Z+ - elpm @1, Z+ + lsl zl + rol zh + rol zh + out RAMPZ, zh + ror zh + elpm @0, Z+ + elpm @1, Z+ I find it improper to damage temp7 which an application programmer may want to use. RAMPZ does not care what you write into bits 1-7. Thanks, Enoch. P/S I have rewritten your usart ISR drivers to support RTS/CTS/DTR in a generic way (using application supplied macros). Works well so far. BTW, I can now upload code using any send-file utility which respects CTS, so bye-bye echo monitoring :-) Will share code if you are interested. ------------------------------------------------------------------------------ This SF.net email is sponsored by Windows: Build for Windows Store. http://p.sf.net/sfu/windows-dev2dev _______________________________________________ Amforth-devel mailing list for http://amforth.sf.net/ Amforth-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/amforth-devel
