Hi Enoch, > Would you be ready to replace the autogenerated readflashcell / > writeflashcell code in device.asm for 128KB architectures as follows:
Some of the 128KB devices use two bits in the RAMPZ register (at least according to the partdescription files). And all of the 256KB devices (obviously). Your patch potentially breaks them all. > P/S I have rewritten your usart ISR drivers to support RTS/CTS/DTR in a > generic way (using application supplied macros). I rewrote (internally) the assembly code with plain forth code: ; : isr-rx USART_DATA c@ ; dup 3 = if cold then \ ctrl-c check ; usart_rx_data usart_rx_in c@ dup >r ; + c! ; r> 1+ usart_rx_mask and usart_rx_in c! ; ; ; setup with ; ' isr-rx URXCaddr int! It the verbatim translation of the existing code, it took (IIRC) a few minutes to write it. It has some possibilities for improvements / factors, that the assembly code does not have. One could be your CTS/RTS (or XON/XOFF) flow control. > BTW, I can now upload code using any send-file utility which respects > CTS, so bye-bye echo monitoring :-) Will share code if you are interested. I am, as long as you use forth ;) Since CTS/RTS use additional hardware a recipe for the cookbook would be great. Matthias ------------------------------------------------------------------------------ This SF.net email is sponsored by Windows: Build for Windows Store. http://p.sf.net/sfu/windows-dev2dev _______________________________________________ Amforth-devel mailing list for http://amforth.sf.net/ Amforth-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/amforth-devel
