On Tue, Nov 21, 2017 at 11:23 PM, Luke Kenneth Casson Leighton <l...@lkcl.net> wrote: > https://pdfs.semanticscholar.org/f6d5/e754da444b7ede6e4eeaf0d61e8cbb82ade9.pdf > > https://arxiv.org/abs/1607.02318 > > so, the compression and something called macro-op fusion results in a > significant reduction in code size that happens also to result in less > cache usage and also faster execution time. how about that, huh? :) >
Yes that was the entire point of risc-v, to make a risc isa with what we learned from the mistakes of the past( there is a video going in depth on the risc-v youtube channel about instruction density that I can't seem to locate right now, but anyway removing the extra step x86-64 has makes perfect sense). Although from your second link the snapdragon 801 example that I gave before is supposed to be slightly denser or equal to the compressed version of risc v, so this alone doesn't seem to explain the difference. Anyway, if those are their targets we'll have to wait and see what they come up with. _______________________________________________ arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netb...@files.phcomp.co.uk
