On Nov 22, 2017, at 10:08, Luke Kenneth Casson Leighton <l...@lkcl.net> wrote: > they're not really optional, they're GNDing VIAs for a couple of > capacitors on the TOP layer, associated with the PMIC area. i'll take > a look, see what they're for: it *might* be possible to move them > direclly south or south east, to the edge of the exclusion area.
If they are grounding power capacitors, don't move them unless you can do so while maintaining (or better yet shrinking) the distance from capacitor pad to via. Low impedance power is precious! > also i just noticed that TX1N/P has that little kink, it turns 45 > degrees anti-clockwise (from the long horizontal straight) about 15mil > late, and i really don't know why :) It seems you decided to split up the extra width needed to accommodate the ground vias between TX0 and the clock lines across all the Northeast bends and then move TX1 and TX0 to avoid running into the ground vias. I see both TX1 and TX0 jogging back to 15mil inter-pair (between pair) spacing after they turn Northeast. Had we closely maintained that spacing in the corner, the bends in TX2 would have pointed through the bends in TX1, TX0, and TXC. Actually, the corner in the northern keep away for the ground fill would look through the corners in TX2, TX1, TX0, TXC, and the southern keep away for ground fill. > less complicated is good.... I agree. I try to avoid unneeded complication. Therefore it comes down to balancing priorities: the most important things generally represent "needed" complexity. Richard _______________________________________________ arm-netbook mailing list arm-netbook@lists.phcomp.co.uk http://lists.phcomp.co.uk/mailman/listinfo/arm-netbook Send large attachments to arm-netb...@files.phcomp.co.uk
